公开(公告)号：US11749623B2

公开(公告)日：2023-09-05

申请号：US17458778

申请日：2021-08-27

申请人： Taiwan Semiconductor Manfuacturing Company, Ltd.

发明人： Meng-Han Lin ,  Chia-En Huang

IPC分类号： H01L23/58 ,  H10B51/20 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L23/564 ,  H10B51/20

摘要： A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

公开(公告)号：US11728338B2

公开(公告)日：2023-08-15

申请号：US17465556

申请日：2021-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Yu Chen ,  Yen Lian Lai

IPC分类号： H01L27/088 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L27/088 ,  H01L23/562 ,  H01L23/585

摘要： Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

公开(公告)号：US11728288B2

公开(公告)日：2023-08-15

申请号：US17458687

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chien-Chang Lee ,  Chia-Ping Lai

IPC分类号： H01L21/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L25/0657 ,  H01L23/562 ,  H01L25/18 ,  H01L2225/06544

摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

公开(公告)号：US11721644B2

公开(公告)日：2023-08-08

申请号：US17372694

申请日：2021-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien Hung Chen ,  Shu-Shen Yeh ,  Po-Chen Lai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3185 ,  H01L23/585 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/35121

摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

公开(公告)号：US20230238340A1

公开(公告)日：2023-07-27

申请号：US18190361

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC分类号： H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/498

CPC分类号： H01L23/585 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/49816

摘要： Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

公开(公告)号：US20230238335A1

公开(公告)日：2023-07-27

申请号：US17850149

申请日：2022-06-27

申请人： SK hynix Inc.

发明人： Won Sun SEO

IPC分类号： H01L23/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/585

摘要： A semiconductor chip includes an integrated circuit disposed in a device region, and a chip guard disposed in a chip sealing region that is an outer portion of the device region. The chip guard includes a first metal layer disposed over a substrate, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, and a barrier pattern extending in a direction towards the substrate from the second metal layer through the interlayer insulating layer. The barrier pattern is disposed to be spaced apart from the first metal layer.

公开(公告)号：US20230215838A1

公开(公告)日：2023-07-06

申请号：US17928318

申请日：2021-05-19

申请人： Siemens Aktiengesellschaft

发明人： Bernd Müller ,  Christian Nachtigall-Schellenberg ,  Jörg Strogies ,  Klaus Wilke

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/92 ,  H01L24/33 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L21/563 ,  H01L23/3185 ,  H01L2224/33183 ,  H01L2224/3303 ,  H01L2224/29191 ,  H01L2924/0715 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/9211 ,  H01L2224/81201 ,  H01L2224/83201 ,  H01L2224/8184 ,  H01L2224/83102 ,  H01L23/585

摘要： Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

公开(公告)号：US20230207500A1

公开(公告)日：2023-06-29

申请号：US18079978

申请日：2022-12-13

申请人： CANON KABUSHIKI KAISHA

发明人： Yasushi Koyama ,  Takeaki Itsuji

IPC分类号： H01L23/66 ,  H01L23/12 ,  H03B5/20 ,  H03B5/12 ,  H03B7/08 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/66 ,  H01L23/12 ,  H03B5/20 ,  H03B5/129 ,  H03B7/08 ,  H01L23/585 ,  H01L24/48 ,  H01L23/3142 ,  H03B2201/0208 ,  H01L2224/48157

摘要： A high-frequency circuit device includes: a chip which includes a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground; a package substrate on which the chip is disposed, a shunt path which is constituted by a package signal conductor which is disposed on an upper surface of the package substrate and is electrically connected to the signal conductor, a package first ground which is electrically connected to the chip ground, and a shunt element which is electrically connected to the package signal conductor and the package first ground; and a package second ground which is disposed at least inside the base of the package substrate or on a back surface of the package substrate, wherein a part of the base, a part of the shunt path, and the package second ground constitute a capacitive structure.

公开(公告)号：US20230207491A1

公开(公告)日：2023-06-29

申请号：US17561353

申请日：2021-12-23

申请人： Intel Corporation

发明人： Kimberly Pierce ,  Marni Nabors ,  Mark Phillips

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06 ,  G03F7/20

CPC分类号： H01L23/585 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0611 ,  G03F7/2004

摘要： Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.

公开(公告)号：US20230197642A1

公开(公告)日：2023-06-22

申请号：US18172208

申请日：2023-02-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yiqi TANG ,  Li JIANG ,  Rajen Manicon MURUGAN

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L23/552

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L23/562 ,  H01L23/552

摘要： In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.