公开(公告)号：US20180252770A1

公开(公告)日：2018-09-06

申请号：US15971304

申请日：2018-05-04

申请人： AT&T Intellectual Property I, L.P.

发明人： Mostafa Tofighbakhsh ,  Thomas A. Anschutz

IPC分类号： G01R31/317 ,  H04L12/26 ,  H04L12/24 ,  G06F11/30

CPC分类号： G01R31/31712 ,  G06F11/3003 ,  G06F11/3093 ,  H04L41/0803 ,  H04L43/12

摘要： Configurable probe blocks for system monitoring are disclosed. Example apparatus disclosed herein include a processor to perform operations including enabling, based on a value of a control word, a first probe input of a probe block, the first probe input mapped to a source of monitored network traffic in a software defined network. Disclosed example apparatus also include configuring, based on the value of the control word, a first trigger condition of the probe block to evaluate the monitored network traffic to determine whether the monitored network traffic has a first characteristic. Disclosed example apparatus further include configuring, based on the value of the control word, a first probe output of the probe block to output a result of the monitored network traffic being evaluated according to the first trigger condition, the first probe output to output the result to a network application of the software defined network.

公开(公告)号：US10012690B2

公开(公告)日：2018-07-03

申请号：US15797058

申请日：2017-10-30

申请人： Texas Instruments Incorporated

发明人： Ramana Tadepalli

IPC分类号： G01R31/10 ,  G01R31/28 ,  G01R31/317

CPC分类号： G01R31/2834 ,  G01R31/31712 ,  G01R31/3172

摘要： An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.

公开(公告)号：US09791509B2

公开(公告)日：2017-10-17

申请号：US14699892

申请日：2015-04-29

申请人： Huawei Technologies Co., Ltd.

发明人： Shichun Zhong ,  Yanbin Luo

IPC分类号： G01R31/3183 ,  G01R31/3177 ,  G01R31/317 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

CPC分类号： G01R31/318371 ,  G01R31/31703 ,  G01R31/31712 ,  G01R31/31718 ,  G01R31/3177 ,  G06F11/0703 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/3024 ,  G06F11/3072 ,  G06F11/3089 ,  G06F11/3471 ,  G06F11/348

摘要： Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.

公开(公告)号：US09557380B2

公开(公告)日：2017-01-31

申请号：US15054565

申请日：2016-02-26

申请人： GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sho-Mo Chen ,  Chien-Cheng Wu

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/31725 ,  G01R31/31712 ,  G01R31/318541

摘要： Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

摘要翻译： 提供扫描触发器和相关方法。 扫描触发器包括数据输入端，扫描输入端，触发电路，第一晶体管和多个第二晶体管。 第一晶体管的栅极耦合到扫描输入端，第二晶体管的栅极通常耦合到使能信号，第一晶体管的漏极和源极和第二晶体管串联耦合到触发器电路，以便 以增加扫描输入端和触发器电路之间的延迟。

公开(公告)号：US20160169973A1

公开(公告)日：2016-06-16

申请号：US14570082

申请日：2014-12-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： STEVE L. LECLERC

IPC分类号： G01R31/317

CPC分类号： G01R31/31701 ,  G01R31/2803 ,  G01R31/2834 ,  G01R31/2851 ,  G01R31/2856 ,  G01R31/2882 ,  G01R31/303 ,  G01R31/31712 ,  G01R31/31718 ,  G01R31/31724 ,  G01R31/318597 ,  G01R31/31907 ,  G01R31/31908

摘要： A test controller controlled by a design entity sends at least one closed type command of a closed loop architecture test flow to an arbiter of a vendor test platform controlled by a vendor entity, wherein the test controller controls nondeterministic testing on a protected integrated circuit (IC) integrated into an electronic assembly, as performed by test equipment hardware within the vendor test platform, without the design entity disclosing an underlying design of the protected IC to the vendor entity. In response to the test controller receiving at least one response of the at least one closed type command, from the arbiter interface passing the at least one closed type command directly through the test equipment hardware to the protected IC, determining, by the test controller, based on the at least one response, a next at least one closed type command of the closed loop architecture test flow to send to the arbiter.

摘要翻译： 由设计实体控制的测试控制器将闭环架构测试流的至少一个闭合类型命令发送到由供应商实体控制的供应商测试平台的仲裁器，其中测试控制器控制受保护集成电路（IC）的非确定性测试 ）集成到电子组件中，由供应商测试平台内的测试设备硬件执行，而设计实体向供应商实体披露受保护IC的底层设计。 响应于测试控制器接收至少一个闭合类型命令的至少一个响应，从仲裁器接口通过至少一个闭合类型命令直接通过测试设备硬件到受保护的IC，由测试控制器确定， 基于所述至少一个响应，所述闭环体系结构测试流的下一个至少一个闭合类型命令发送到所述仲裁器。

公开(公告)号：US09310435B2

公开(公告)日：2016-04-12

申请号：US14519484

申请日：2014-10-21

申请人： GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sho-Mo Chen ,  Chien-Cheng Wu

IPC分类号： H03K3/00 ,  G01R31/3185

CPC分类号： G01R31/31725 ,  G01R31/31712 ,  G01R31/318541

摘要： Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

摘要翻译： 提供扫描触发器和相关方法。 扫描触发器包括数据输入端，扫描输入端，触发电路，第一晶体管和多个第二晶体管。 第一晶体管的栅极耦合到扫描输入端，第二晶体管的栅极通常耦合到使能信号，第一晶体管的漏极和源极和第二晶体管串联耦合到触发器电路，以便 以增加扫描输入端和触发器电路之间的延迟。

公开(公告)号：US20150113345A1

公开(公告)日：2015-04-23

申请号：US14519484

申请日：2014-10-21

申请人： GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sho-Mo Chen ,  Chien-Cheng Wu

IPC分类号： G01R31/3177

CPC分类号： G01R31/31725 ,  G01R31/31712 ,  G01R31/318541

摘要： Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

摘要翻译： 提供扫描触发器和相关方法。 扫描触发器包括数据输入端，扫描输入端，触发电路，第一晶体管和多个第二晶体管。 第一晶体管的栅极耦合到扫描输入端，第二晶体管的栅极通常耦合到使能信号，第一晶体管的漏极和源极和第二晶体管串联耦合到触发器电路，以便 以增加扫描输入端和触发器电路之间的延迟。

公开(公告)号：US08195994B2

公开(公告)日：2012-06-05

申请号：US13091721

申请日：2011-04-21

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3172 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

摘要翻译： 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。

公开(公告)号：US07902847B2

公开(公告)日：2011-03-08

申请号：US12482560

申请日：2009-06-11

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G01R31/02

CPC分类号： G01R31/318335 ,  G01R31/31712 ,  G01R31/31724 ,  G01R31/318511

摘要： A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.

摘要翻译： 半导体器件包括：命令控制电路，用于解码命令信号以输出测试信号和正常控制信号; 用于响应于正常控制信号执行预定操作的正常电路; 以及用于测试响应于测试信号在普通电路中提供的单元的电特性的测试电路。

公开(公告)号：US07865791B2

公开(公告)日：2011-01-04

申请号：US12560697

申请日：2009-09-16

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3172 ,  G01R31/31701 ,  G01R31/31705 ,  G01R31/31712 ,  G01R31/31713 ,  G01R31/31722 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318364 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

摘要翻译： 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。