公开(公告)号：US20240223085A1

公开(公告)日：2024-07-04

申请号：US18607702

申请日：2024-03-18

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chia-Chun Chang ,  Alan Roth ,  Eric Soenen ,  Tysh-Bin Liu

IPC分类号： H02M3/158 ,  H02M1/08 ,  H02M1/38 ,  H02M3/157 ,  H02M1/00

CPC分类号： H02M3/158 ,  H02M1/08 ,  H02M1/38 ,  H02M3/157 ,  H02M1/0009 ,  H02M1/0029

摘要： Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

公开(公告)号：US20240222332A1

公开(公告)日：2024-07-04

申请号：US18604542

申请日：2024-03-14

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Wen-Tuo Huang

IPC分类号： H01L25/065 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06596

摘要： Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

公开(公告)号：US12027475B2

公开(公告)日：2024-07-02

申请号：US18338596

申请日：2023-06-21

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chien-Chang Lee ,  Chia-Ping Lai

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L25/0657 ,  H01L23/562 ,  H01L25/18 ,  H01L2225/06544

摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

公开(公告)号：US20240215217A1

公开(公告)日：2024-06-27

申请号：US18596501

申请日：2024-03-05

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Gerben DOORNBOS ,  Marcus Johannes Henricus VAN DAL

IPC分类号： H10B12/00 ,  H01L29/06 ,  H01L29/225 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H10B12/033 ,  H01L29/0673 ,  H01L29/225 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/315 ,  H10B12/395 ,  H10B12/482 ,  H01L2029/7858

摘要： A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

公开(公告)号：US12021137B2

公开(公告)日：2024-06-25

申请号：US17578569

申请日：2022-01-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Oreste Madia

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/02496 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/44 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/7869 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02488

摘要： A method of forming a semiconductor device may include depositing a NiAl layer on a substrate, oxidizing the NiAl layer to form a bilayer including a NiO semiconducting material layer and an AlOx layer on the NiO semiconducting material layer, forming a semiconductor layer including the NiO semiconducting material layer, the semiconductor layer also including a channel region, and forming a gate dielectric on the channel region of the semiconductor layer.

公开(公告)号：US12021084B2

公开(公告)日：2024-06-25

申请号：US18344571

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tzu-Chung Wang

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

公开(公告)号：US12018981B2

公开(公告)日：2024-06-25

申请号：US18202703

申请日：2023-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chewn-Pu Jou ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Lan-Chou Cho

IPC分类号： G01J1/04 ,  G01J1/42 ,  G01J1/44 ,  G02B6/42

CPC分类号： G01J1/0422 ,  G01J1/0474 ,  G01J1/4228 ,  G01J1/44 ,  G02B6/4206

摘要： A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation. The first detected radiation is phase aligned with the second detected radiation.

公开(公告)号：US12014976B2

公开(公告)日：2024-06-18

申请号：US18191147

申请日：2023-03-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Kuo Lung Pan ,  Yu-Chia Lai ,  Teng-Yuan Lo ,  Mao-Yen Chang ,  Po-Yuan Teng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/16

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L25/16 ,  H01L25/50

摘要： A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

公开(公告)号：US20240194589A1

公开(公告)日：2024-06-13

申请号：US18581165

申请日：2024-02-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shao-Kuan LEE ,  Hai-Ching CHEN ,  Hsin-Yen HUANG ,  Shau-Lin SHUE ,  Cheng-Chin LEE

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/53295

摘要： A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

公开(公告)号：US12005481B2

公开(公告)日：2024-06-11

申请号：US17723982

申请日：2022-04-19

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Ying-Hao Wang ,  Chien-Lung Chen ,  Chia-Han Chuang ,  Jhe-Hong Wang ,  Chien-Chi Tzeng

IPC分类号： B08B3/02 ,  H01L21/677 ,  B05B9/03 ,  B05B13/02 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

CPC分类号： B08B3/022 ,  H01L21/67706 ,  B05B9/035 ,  B05B13/0221 ,  H01L23/3675 ,  H01L25/0652 ,  H01L25/18

摘要： An embodiment system, configured to clean a semiconductor package assembly, may include a sprayer device including a plurality of nozzles configured to direct a pressurized cleaning fluid toward the semiconductor package assembly; a conveyor configured to move the semiconductor package assembly relative to the sprayer device along a first direction; and a dryer spatially displaced from the sprayer device and configured to direct a pressurized gas flow toward the semiconductor package assembly to remove cleaning fluid introduced by the sprayer device. Each of the plurality of nozzles may be displaced from one another along a second direction to thereby generate respective separate spray distribution patterns. Adjacent nozzles may be further displaced from one another along a third direction to thereby a reduce an overlap of adjacent spray distribution patterns relative to a configuration in which the adjacent nozzles are not displaced from one another along the third direction.