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    Gate air spacer for fin-like field effect transistor
    32.
    发明授权
    Gate air spacer for fin-like field effect transistor 有权

    公开(公告)号：US12211922B2

    公开(公告)日：2025-01-28

    申请号：US18355073

    申请日：2023-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Ning Yao ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L29/49 ,  H01L21/28 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

    Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

    VERTICAL DRAM STRUCTURE AND METHOD
    33.
    发明申请
    VERTICAL DRAM STRUCTURE AND METHOD 有权

    公开(公告)号：US20240389304A1

    公开(公告)日：2024-11-21

    申请号：US18788379

    申请日：2024-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H10B12/00 ,  H01L29/10

    Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

    Memory array including epitaxial source lines and bit lines
    40.
    发明授权
    Memory array including epitaxial source lines and bit lines 有权

    公开(公告)号：US11974441B2

    公开(公告)日：2024-04-30

    申请号：US17138152

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

    CPC classification number: H10B51/20 ,  H01L29/0653 ,  H01L29/0669 ,  H10B51/10

    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

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