公开(公告)号：US20180342420A1

公开(公告)日：2018-11-29

申请号：US15605995

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76843 ,  H01L23/535 ,  H01L29/4983 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first spacer, a second spacer, and a first contact plug. The gate structure is disposed on the semiconductor substrate. The first spacer is disposed around the gate structure. The second spacer is disposed on the first spacer. The first contact plug lands on the second spacer and the gate structure.

公开(公告)号：US20170256696A1

公开(公告)日：2017-09-07

申请号：US15057734

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Yu-Ming LIN

IPC: H01L35/32

CPC classification number: H01L35/325

Abstract: Thermoelectric generators are provided. A thermoelectric generator includes a thermoelectric structure and a rectifier bridge. The thermoelectric structure includes a semiconductor substrate, a first metal layer disposed on the semiconductor substrate, a dielectric layer disposed on the first metal layer, a second metal layer disposed on the dielectric layer, and a plurality of first materials disposed in the dielectric layer and coupled between the first electrodes and the second electrodes. The first metal layer includes a plurality of first electrodes. The second metal layer includes a plurality of second electrodes. The rectifier bridge coupled to the thermoelectric structure provides an output voltage according to electrical energy from the thermoelectric structure. The thermoelectric structure provides the electrical energy according to a temperature difference between the first metal layer and the second metal layer. The first material is a thermoelectric material.

公开(公告)号：US20250142926A1

公开(公告)日：2025-05-01

申请号：US19009482

申请日：2025-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H10D64/23 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20250056862A1

公开(公告)日：2025-02-13

申请号：US18932293

申请日：2024-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

公开(公告)号：US20220367268A1

公开(公告)日：2022-11-17

申请号：US17874170

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Yu-Ming LIN ,  Chih-Hao WANG ,  Wai-Yi LIEN

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, an interlayer dielectric (ILD) layer, an etch stop layer, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The ILD layer surrounds the conductive structure and over the gate electrode. The etch stop layer is over the conductive structure and the ILD layer. The etch stop layer comprises a material different from that of the ILD layer. A dielectric liner at a sidewall the conductive structure. The dielectric liner extends from the top surface of the source/drain contact to a bottom surface of the etch stop layer.

公开(公告)号：US20220181216A1

公开(公告)日：2022-06-09

申请号：US17681588

申请日：2022-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a side of the dummy gate. The dummy gate is replaced with a gate structure, such that that first gate spacer is on a side of the gate structure. The gate structure is etched back. After etching back the gate structure, a top portion of the first gate spacer is removed. A second gate spacer is formed over a remaining portion of the first gate spacer. After forming the second gate spacer, a dielectric cap is formed over the gate structure.

公开(公告)号：US20210351080A1

公开(公告)日：2021-11-11

申请号：US17168047

申请日：2021-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ming-Hsi YEH ,  Shahaji B. MORE ,  Chandrashekhar Prakash SAVANT ,  Chih-Hsin KO ,  Clement Hsingjen WANN

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/324 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

公开(公告)号：US20200381291A1

公开(公告)日：2020-12-03

申请号：US16947932

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20200279924A1

公开(公告)日：2020-09-03

申请号：US16875869

申请日：2020-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Yu-Ming LIN ,  Chao-Hsin WU ,  Hsun-Ming CHANG ,  Samuel C. PAN

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40 ,  H01L21/385 ,  H01L29/10 ,  H01L29/778 ,  H01L29/861 ,  H01L29/45 ,  H01L29/267

Abstract: A device includes a phosphide-containing structure, a dopant source layer and a conductive contact. The phosphide-containing structure has a first chemical element in a compound with phosphorus. The dopant source layer is over the phosphide-containing structure and has a second chemical element the same as the first chemical element. The conductive contact is over the dopant source layer.

公开(公告)号：US20200273748A1

公开(公告)日：2020-08-27

申请号：US16871983

申请日：2020-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Yu-Ming LIN ,  Chih-Hao WANG ,  Wai-Yi LIEN

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole after removing the portion of the source/drain contact, and forming a conductive structure in the hole.