公开(公告)号：US20180308953A1

公开(公告)日：2018-10-25

申请号：US16010641

申请日：2018-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/205 ,  H01L23/31 ,  H01L23/29 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US20180248009A1

公开(公告)日：2018-08-30

申请号：US15959459

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/861

Abstract: The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.

公开(公告)号：US10020376B2

公开(公告)日：2018-07-10

申请号：US15613660

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L23/29 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L23/31 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US09685525B2

公开(公告)日：2017-06-20

申请号：US15234590

申请日：2016-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L23/29 ,  H01L23/31 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US20160141404A1

公开(公告)日：2016-05-19

申请号：US14540250

申请日：2014-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Wei Tsai ,  King-Yuen Wong ,  Han-Chin Chiu ,  Sheng-de Liu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462

Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.

Abstract translation: 提供了采用栅极保护层的高电子迁移率晶体管（HEMT）器件。 衬底具有布置在衬底上的沟道层，并且具有布置在沟道层上的势垒层。 通道和阻挡层限定了异质结，并且栅极结构被布置在阻挡层的栅极区域的上方。 栅极结构包括布置在盖上的栅极，其中盖设置在阻挡层上。 栅极保护层沿着盖的侧壁布置并且布置在栅极的相对表面和栅极之下的栅极下方。 有利地，栅极保护层钝化栅极，减少沿着盖的侧壁的泄漏电流，并且提高器件可靠性和阈值电压均匀性。 还提供了一种用于制造HEMT装置的方法。

公开(公告)号：US20150060861A1

公开(公告)日：2015-03-05

申请号：US14016328

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  King-Yuen Wong ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462

Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

Abstract translation: 本公开的一些实施例涉及具有良好的界面和体介电特性的混合栅极介电层。 表面捕集阱可能会降低器件性能，并在III-N HEMT中引起较大的阈值电压漂移。 本公开使用混合ALD（原子层沉积） - 氧化物层，其是基于H 2 O和O 3 / O 2的氧化物层的组合，其为III-N器件提供良好的界面和良好的体积介电性质。 H 2 O基氧化物层与III-N表面提供良好的界面，而O 3 / O 2基氧化物层提供良好的体积性质。