公开(公告)号：US20160145095A1

公开(公告)日：2016-05-26

申请号：US14639530

申请日：2015-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Heng Tsai ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Tzu-Heng Wu ,  Wei-Cheng Shen

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/0048

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.

Abstract translation: 三维（3D）集成电路（IC）包括第一IC和第二IC。 第一IC包括MEMS器件和第一接合结构。 第二IC包括第二接合结构。 第一和第二接合结构被结合在一起以将第一IC耦合到第二IC。 在距离第一IC最近的第二IC的表面上设置保形阻挡层。 蚀刻隔离结构被布置在第二IC的表面下方并且包围一个牺牲区域，该牺牲区域被布置在第二接合结构的任一侧上并且被布置在第二IC中。

公开(公告)号：US11730058B2

公开(公告)日：2023-08-15

申请号：US16413839

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H01L41/193 ,  H01L41/08 ,  H01L41/113 ,  D01F6/62 ,  H10N30/00 ,  H10N30/04 ,  H10N30/067 ,  H10N30/87 ,  H10N30/063

CPC classification number: H10N30/10513 ,  H10N30/04 ,  H10N30/067 ,  H10N30/877 ,  H10N30/063

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

公开(公告)号：US11588095B2

公开(公告)日：2023-02-21

申请号：US16421810

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: H01L41/113 ,  G01N27/414 ,  H01L41/33 ,  H01L41/053 ,  H01L41/27 ,  H01L41/047

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

公开(公告)号：US11365115B2

公开(公告)日：2022-06-21

申请号：US16558539

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fan Hu ,  Chun-Ren Cheng ,  Hsiang-Fu Chen ,  Wen-Chuan Tai

IPC: B81B3/00 ,  B81C1/00

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

公开(公告)号：US11320395B2

公开(公告)日：2022-05-03

申请号：US16900989

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Jui-Cheng Huang ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Yu-Jie Huang ,  Fu-Chun Huang

IPC: G01N27/414 ,  H01L23/31 ,  H01L23/522 ,  H01L23/64 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/29

Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.

公开(公告)号：US11289568B2

公开(公告)日：2022-03-29

申请号：US16410259

申请日：2019-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Wen-Chuan Tai ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Anderson Lin ,  Fu-Chun Huang ,  Chun-Ren Cheng ,  Ivan Hua-Shu Wu ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01L49/02 ,  H01L23/58 ,  H01L23/00

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

公开(公告)号：US20210389273A1

公开(公告)日：2021-12-16

申请号：US16900989

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Jui-Cheng Huang ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Yu-Jie Huang ,  Fu-Chun Huang

IPC: G01N27/414 ,  H01L23/31 ,  H01L23/522 ,  H01L23/29 ,  H01L23/64 ,  H01L29/786 ,  H01L21/8234

Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.

公开(公告)号：US10984211B1

公开(公告)日：2021-04-20

申请号：US16656882

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: G06K9/00 ,  H01L41/113 ,  G01N27/414

Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.

公开(公告)号：US20200072789A1

公开(公告)日：2020-03-05

申请号：US16679015

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao LIU ,  Chun-Ren Cheng ,  Ching-Ray Chen ,  Yi-Hsien Chang ,  Fei-Lung Lai ,  Chun-Wen Cheng

IPC: G01N27/414 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

公开(公告)号：US09493346B2

公开(公告)日：2016-11-15

申请号：US14445226

申请日：2014-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Shen ,  Yi-Hsien Chang ,  Yi Heng Tsai ,  Tzu-Heng Wu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238

Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.

Abstract translation: 提供集成电路（IC）结构。 IC结构包括IC基板，其包括通过布置在其上的导电互连结构耦合在一起的有源器件。 导电互连结构包括布置在相邻的水平导电层之间的一系列水平导电层和电介质区域。 导电互连结构包括具有平坦顶表面区域的最上面的导电水平区域。 MEMS基板布置在IC基板上方，并且包括柔性或可移动的结构，其以施加到柔性或可移动结构的力相应地弯曲或移动。 IC基板的有源器件被布置成建立分析电路，以便于电测量最上面的导电水平区域和柔性或可移动结构之间的电容。