公开(公告)号：US20230411494A1

公开(公告)日：2023-12-21

申请号：US18366908

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L21/823431 ,  H01L29/785 ,  H01L21/823468

Abstract: A method includes forming a fin over a substrate, forming an isolation structure on the substrate, and forming first and second mandrel patterns over the fin. The fin extends upwardly through the isolation structure. The fin extends lengthwise along a first direction, and each of the first and second mandrel patterns extends lengthwise along a second direction perpendicular to the first direction. The method also includes depositing a sacrificial feature between the first and second mandrel patterns, removing the first and second mandrel patterns, forming a spacer layer in physical contact with sidewalls of the sacrificial feature, removing the sacrificial feature to form a trench, and forming a metal gate stack in the trench. The sacrificial feature extends lengthwise along the second direction.

公开(公告)号：US11824101B2

公开(公告)日：2023-11-21

申请号：US17705508

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature over the semiconductor substrate, a fin protruding from the semiconductor substrate and through the isolation feature, a gate stack over and engaging the fin, and a gate spacer on sidewalls of the gate stack. A bottom portion of the sidewalls of the gate stack tilts inwardly towards the gate stack.

公开(公告)号：US11444202B2

公开(公告)日：2022-09-13

申请号：US16745340

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Chien-Ning Yao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.

公开(公告)号：US11189708B2

公开(公告)日：2021-11-30

申请号：US16656014

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chien-Ning Yao ,  Chi-On Chui

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.

公开(公告)号：US11081395B2

公开(公告)日：2021-08-03

申请号：US16286558

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L21/764

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US20210217870A1

公开(公告)日：2021-07-15

申请号：US16741767

申请日：2020-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/285 ,  H01L27/092

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

公开(公告)号：US20210098458A1

公开(公告)日：2021-04-01

申请号：US16805858

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Chun-Heng Chen ,  Ming-Ho Lin ,  Chi-On Chui

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02

Abstract: Provided are a deposition method, a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate and a dielectric structure. The substrate includes at least one fin thereon. The dielectric structure covers the at least one fin. A thickness of the dielectric structure located on a top surface of the at least one fin is greater than a thickness of the dielectric structure located on a sidewall of the at least one fin. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is conformally disposed on the at least one fin. The second dielectric layer is disposed on the first dielectric layer over the top surface of the at least one fin. A thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

公开(公告)号：US10861968B1

公开(公告)日：2020-12-08

申请号：US16427078

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/24 ,  H01L29/66 ,  H01L29/40 ,  H01L21/467

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a negative capacitance (NC) material. The semiconductor device structure also includes a gate electrode layer, a gate dielectric structure, a source feature, and a drain feature. The gate dielectric structure covers the top surface and the opposing sidewall surfaces of the fin structure. The gate electrode layer is formed over the gate dielectric structure. The source feature and the drain feature are formed in and protrude from the fin structure, and separated from each other by the gate electrode layer.

公开(公告)号：US10468529B2

公开(公告)日：2019-11-05

申请号：US15646386

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui

IPC: H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.

公开(公告)号：US20180301558A1

公开(公告)日：2018-10-18

申请号：US15487559

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Chi-On Chui

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.