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公开(公告)号：US10971544B2
公开(公告)日：2021-04-06
申请号：US16045237
申请日：2018-07-25
Inventor： Chung-Cheng Chou , Ya-Chen Kao , Tien-Wei Chiang
Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
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公开(公告)号：US20210096586A1
公开(公告)日：2021-04-01
申请号：US17010064
申请日：2020-09-02
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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公开(公告)号：US20180350877A1
公开(公告)日：2018-12-06
申请号：US16045237
申请日：2018-07-25
Inventor： Chung-Cheng Chou , Ya-Chen Kao , Tien-Wei Chiang
CPC classification number: H01L27/228 , H01L43/10 , H01L43/12
Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
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公开(公告)号：US10014469B2
公开(公告)日：2018-07-03
申请号：US15437977
申请日：2017-02-21
Inventor： Po-Hao Lee , Chung-Cheng Chou , Wen-Ting Chu
IPC: H01L45/00
CPC classification number: H01L45/1608 , H01L45/08 , H01L45/122 , H01L45/124 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1683
Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.
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35.发明授权Low dropout regulator with an amplifier stage, current mirror, and auxiliary current source and related method 有权具有放大器级，电流镜和辅助电流源的低压差稳压器及相关方法公开(公告)号：US09323259B2
公开(公告)日：2016-04-26
申请号：US14080238
申请日：2013-11-14
Inventor： Chung-Cheng Chou , Po-Hao Lee
CPC classification number: G05F1/468 , G05F1/46 , G05F1/575 , H02M1/12 , H02M3/3382
Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.
Abstract translation: 一种设备被配置为提供低压差调节。 放大器级包括电连接到器件的输出的第一晶体管和第二晶体管。 电流镜包括电连接到第二晶体管的第三晶体管和与第三晶体管电连接的第四晶体管。 辅助电流源具有电连接到第四晶体管的栅电极的控制端子。 下拉级包括具有电连接到第一晶体管的漏电极的栅电极的第五晶体管和与第四晶体管的栅电极电连接的栅电极的第六晶体管。 上拉晶体管具有电连接到第五晶体管的漏电极的栅电极。 第一电容器具有电连接到第一晶体管的栅电极的第一端子。
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Patent Agency Ranking
公开(公告)号：US20160013756A1
公开(公告)日：2016-01-14
申请号：US14329866
申请日：2014-07-11
Inventor： Chung-Cheng Chou
CPC classification number: H03F3/505 , H03F3/45183 , H03F2200/135 , H03F2200/456 , H03F2200/555 , H03F2203/45674
Abstract: A device includes an amplifier stage, a source follower, a resistive device, and a transistor. The source follower has an input terminal electrically coupled to an internal node of the amplifier stage, and an output terminal electrically coupled to an input terminal of the amplifier stage and an output terminal of the device. The resistive device has a first terminal electrically coupled to the output terminal of the device. The transistor is electrically coupled to a second terminal of the resistive device and the amplifier stage.
Abstract translation: 器件包括放大器级，源极跟随器，电阻器件和晶体管。 源极跟随器具有电耦合到放大器级的内部节点的输入端子和电耦合到放大器级的输入端子和该器件的输出端子的输出端子。 电阻器件具有电耦合到器件的输出端子的第一端子。 晶体管电耦合到电阻器件和放大器级的第二端子。
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公开(公告)号：US09224464B2
公开(公告)日：2015-12-29
申请号：US14176820
申请日：2014-02-10
Inventor： Chung-Cheng Chou , Po-Hao Lee , Jonathan Tehan Chen
CPC classification number: G11C13/004 , G11C7/12 , G11C2013/005 , G11C2013/0054 , G11C2213/79
Abstract: A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.
Abstract translation: 一种装置包括一个存储位单元，一个第一电流源和一个电连接到存储位单元和第一个电流源的电流比较器。 第一晶体管具有电连接到第一电压供应节点的第一端子，电连接到控制器的控制端子和电连接到存储器位单元和电流比较器的第二端子。 读出放大器电连接到电流比较器和参考电流发生器。
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公开(公告)号：US20150228333A1
公开(公告)日：2015-08-13
申请号：US14176820
申请日：2014-02-10
Inventor： Chung-Cheng Chou , Po-Hao Lee , Jonathan Tehan Chen
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/12 , G11C2013/005 , G11C2013/0054 , G11C2213/79
Abstract: A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.
Abstract translation: 一种装置包括一个存储位单元，一个第一电流源和一个电连接到存储器单元和第一个电流源的电流比较器。 第一晶体管具有电连接到第一电压供应节点的第一端子，电连接到控制器的控制端子和电连接到存储器位单元和电流比较器的第二端子。 读出放大器电连接到电流比较器和参考电流发生器。
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39.发明授权公开(公告)号：US08619463B2
公开(公告)日：2013-12-31
申请号：US13676389
申请日：2012-11-14
Inventor： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
CPC classification number: G11C7/00 , G11C7/20 , G11C8/08 , G11C11/413 , G11C2207/2254
Abstract: A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.
Abstract translation: 包括耦合到写位线或字线的电容器的存储器和被配置为初始化电容器和写位线或字线之间的第一节点处的电压电平的初始化器。 存储器还包括可控的初始电平调节器，其被配置为响应于脉冲调节电容器的一个端子处的第二节点的电压电平。 电容器被配置为在与第一节点相对的端子处的第三节点处接收升压信号。 升压信号被配置为响应于升压信号改变写位线或字线的电压电平。
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公开(公告)号：US12248331B2
公开(公告)日：2025-03-11
申请号：US17877115
申请日：2022-07-29
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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