公开(公告)号：US20240258117A1

公开(公告)日：2024-08-01

申请号：US18586989

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53209

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

公开(公告)号：US20240120200A1

公开(公告)日：2024-04-11

申请号：US18543432

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/76877

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

公开(公告)号：US11849645B2

公开(公告)日：2023-12-19

申请号：US17833688

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/10 ,  H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

公开(公告)号：US20220376169A1

公开(公告)日：2022-11-24

申请号：US17814917

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: A memory device includes a bottom electrode, a tunneling junction disposed over the bottom electrode, and a top electrode disposed over the tunneling junction. The top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer. The first and second top electrode layers include different material compositions. The first top electrode layer is thinner than the tunneling junction, and the second top electrode layer is thicker than the tunneling junction.

公开(公告)号：US11355701B2

公开(公告)日：2022-06-07

申请号：US17001282

申请日：2020-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

公开(公告)号：US11302641B2

公开(公告)日：2022-04-12

申请号：US16898705

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US20220013403A1

公开(公告)日：2022-01-13

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11171052B2

公开(公告)日：2021-11-09

申请号：US16396965

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.

公开(公告)号：US11139236B2

公开(公告)日：2021-10-05

申请号：US16547750

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Hsin-Chieh Yao ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.

公开(公告)号：US20210183654A1

公开(公告)日：2021-06-17

申请号：US17189130

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L21/033 ,  H01L21/768

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.