公开(公告)号：US11678488B2

公开(公告)日：2023-06-13

申请号：US17515981

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/535 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device including: a substrate including a cell array region and a connection region; and an electrode structure extending along a first direction from the cell array region to the connection region and is a plurality of electrodes vertically stacked OD the substrate, each of the electrodes including an electrode portion on the cell array region and a pad portion on the connection region, wherein the electrodes include a first electrode located at a first level from the substrate and a second electrode located at a second level from the substrate, the second level being higher than the first level, and the pad portion of the first electrode is closer to the cell array region than the pad portion of the second electrode.

公开(公告)号：US20220181273A1

公开(公告)日：2022-06-09

申请号：US17367082

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Kwon ,  Seokcheon Baek ,  Younghwan Son

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor device includes first and second gate electrodes stacked and spaced apart from each other in a first direction on a first region of a substrate, and extending in staircase form in a second direction on a second region of the substrate, the second gate electrodes disposed on the first gate electrodes; a first support structure penetrating the first gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level lower than a level of a lowermost second gate electrode among the second gate electrodes; a second support structure penetrating at least one of the first and second gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level higher than a level of un uppermost second gate electrode among the second gate electrodes.

公开(公告)号：US11271003B2

公开(公告)日：2022-03-08

申请号：US16856560

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US20210020648A1

公开(公告)日：2021-01-21

申请号：US16856560

申请日：2020-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H01L27/11556 ,  H01L29/788 ,  G11C5/02

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US10861876B2

公开(公告)日：2020-12-08

申请号：US16846933

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon Lim ,  Hwan Lee

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/105 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

公开(公告)号：US10153295B2

公开(公告)日：2018-12-11

申请号：US15613602

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.