公开(公告)号：US11251070B2

公开(公告)日：2022-02-15

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US10373960B2

公开(公告)日：2019-08-06

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/28 ,  H01L21/71 ,  H01L27/108 ,  H01L29/792 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US20190214391A1

公开(公告)日：2019-07-11

申请号：US16053315

申请日：2018-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US20190206875A1

公开(公告)日：2019-07-04

申请号：US16295562

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US10332842B2

公开(公告)日：2019-06-25

申请号：US16026937

申请日：2018-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

IPC: H01L23/544 ,  H01L27/108

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US09960170B1

公开(公告)日：2018-05-01

申请号：US15614077

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Kiseok Lee ,  Keunnam Kim ,  Bong-Soo Kim ,  Jemin Park ,  Chan-Sic Yoon ,  Yoosang Hwang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.

公开(公告)号：US20180019244A1

公开(公告)日：2018-01-18

申请号：US15646380

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/762 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L27/10814 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/76224 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.

公开(公告)号：US09184136B2

公开(公告)日：2015-11-10

申请号：US14141947

申请日：2013-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Daeik Kim ,  Kang-Uk Kim ,  Nara Kim ,  Jemin Park ,  Kyuhyun Lee ,  Hyun-Woo Chung ,  Gyoyoung Jin ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L23/544 ,  H01L23/48 ,  H01L21/683 ,  H01L27/06 ,  H01L27/146 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。