SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME

    公开(公告)号:US20220157823A1

    公开(公告)日:2022-05-19

    申请号:US17592555

    申请日:2022-02-04

    Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.

    METHOD OF FABRICATING GRAPHENE NANO-MESH
    35.
    发明申请
    METHOD OF FABRICATING GRAPHENE NANO-MESH 有权
    制作石墨纳米网的方法

    公开(公告)号:US20170069436A1

    公开(公告)日:2017-03-09

    申请号:US15066780

    申请日:2016-03-10

    Abstract: Example embodiments relate to a method of fabricating a graphene nano-mesh by selectively growing an oxide layer on a defect site of a graphene layer and etching the oxide layer to form the graphene nano-mesh. The method includes forming a graphene layer on a catalyst layer, forming an oxide layer on a defect site of the graphene layer, forming the graphene nano-mesh including a plurality of openings by etching the oxide layer, and transferring, after removing the catalyst layer, the graphene nano-mesh onto a substrate.

    Abstract translation: 示例性实施例涉及通过选择性地生长石墨烯层的缺陷部位上的氧化物层并蚀刻氧化物层以形成石墨烯纳米网来制造石墨烯纳米网的方法。 该方法包括在催化剂层上形成石墨烯层,在石墨烯层的缺陷部位形成氧化层,通过蚀刻氧化层形成包括多个开口的石墨烯纳米网,并且在除去催化剂层之后转移 ,石墨烯纳米网到基底上。

    WEARABLE ELECTRONIC DEVICE
    36.
    发明申请

    公开(公告)号:US20250076925A1

    公开(公告)日:2025-03-06

    申请号:US18954022

    申请日:2024-11-20

    Abstract: An electronic device includes: a frame including a side wall and at least partially forming an antenna; a bracket provided within the frame; a first printed circuit board provided on the bracket and including at least one grounding portion; a second printed circuit board provided within the frame; and a screw, where the second printed circuit board includes: a first portion coupled to the first printed circuit board; an extension portion extending from the first portion between the side wall of the frame and the bracket; a second portion extending from the extension portion between the first printed circuit board and the bracket; and a conductive trace extending from the first portion to the second portion through the extension portion, and where the conductive trace is electrically connected to the at least one grounding portion of the first printed circuit board in the second portion.

    ELECTRICAL DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

    公开(公告)号:US20240088203A1

    公开(公告)日:2024-03-14

    申请号:US18512648

    申请日:2023-11-17

    CPC classification number: H01L28/56 H01L28/60 H10B12/315 H10B12/34

    Abstract: Provided is a semiconductor device including a lower electrode, an upper electrode isolated from direct contact with the lower electrode, and a dielectric layer between the lower electrode and the upper electrode, the dielectric layer comprising a first metal oxide area, a second metal oxide area, and a third metal oxide area. The third metal oxide area is between the first metal oxide area and the second metal oxide area, and includes boron and one or more metal elements selected from aluminum (Al), magnesium (Mg), silicon (Si), or beryllium (Be). In the third metal oxide area, a content of boron (B) is less than or equal to a content of the metal elements of Al, Mg, Si, and/or Be.

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