公开(公告)号：US10153037B2

公开(公告)日：2018-12-11

申请号：US15885449

申请日：2018-01-31

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C8/08 ,  G11C8/06

Abstract: A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

公开(公告)号：US10120741B2

公开(公告)日：2018-11-06

申请号：US15710803

申请日：2017-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Yoshikazu Saito

IPC: G06F7/02 ,  H03M13/00 ,  G06F11/07

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

公开(公告)号：US09928901B2

公开(公告)日：2018-03-27

申请号：US15619821

申请日：2017-06-12

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

公开(公告)号：US09922703B2

公开(公告)日：2018-03-20

申请号：US15481345

申请日：2017-04-06

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C8/16 ,  G11C7/22 ,  G11C7/10 ,  G11C8/00 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418

Abstract: A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.

公开(公告)号：US09830980B2

公开(公告)日：2017-11-28

申请号：US15465300

申请日：2017-03-21

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Miyanishi ,  Yuichiro Ishii ,  Yoshisato Yokoyama

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

公开(公告)号：US09437283B2

公开(公告)日：2016-09-06

申请号：US14847365

申请日：2015-09-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro Ishii

IPC: G11C5/14 ,  G11C11/419 ,  G11C11/412 ,  G11C7/20

CPC classification number: G11C11/418 ,  G11C5/147 ,  G11C7/20 ,  G11C11/412 ,  G11C11/419

Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

Abstract translation: 所公开的发明提供了一种半导体存储装置，其独立于上电序列而不产生故障。 半导体存储装置包括用于存储单元的第一电源，独立于第一电源而导通的第二电源，并且被提供给电耦合到存储单元的外围电路，以及字线电平固定电路 用于固定根据第一电源的开启而工作的字线的电平。 字线电平固定电路包括多个电平固定晶体管，它们分别被提供以对应于字线并且被设置在一个字线和一个固定电位之间，而电平固定控制电路根据输入端 响应于第二电源的接通的信号。

公开(公告)号：US09390789B2

公开(公告)日：2016-07-12

申请号：US14942861

申请日：2015-11-16

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract translation: 半导体存储装置包括由驱动晶体管，转移晶体管和负载晶体管组成的SRAM存储单元，连接到与存储单元连接的位线的I / O电路，以及操作模式控制电路， 在恢复待机模式和正常操作模式之间的I / O电路的模式，其中I / O电路包括将数据写入位线的写入驱动器，从位线读取数据的读出放大器，插入的第一开关 在位线和写入驱动器之间，插入在位线和读出放大器之间的第二开关，预充电位线的预充电电路，以及根据信号控制第一和第二开关和预充电电路的控制电路 从操作模式控制电路。

公开(公告)号：US08879334B2

公开(公告)日：2014-11-04

申请号：US13750328

申请日：2013-01-25

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Yoshikazu Saito ,  Shinji Tanaka ,  Koji Nii

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/16 ,  G11C7/22 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

公开(公告)号：US10825814B2

公开(公告)日：2020-11-03

申请号：US16287570

申请日：2019-02-27

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Yuichiro Ishii

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

公开(公告)号：US10706917B2

公开(公告)日：2020-07-07

申请号：US16176299

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji Nii ,  Yuichiro Ishii ,  Yohei Sawada ,  Makoto Yabuuchi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12

Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.