公开(公告)号：US20180277657A1

公开(公告)日：2018-09-27

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768

CPC classification number: H01L29/66621 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/76822 ,  H01L29/20 ,  H01L29/402 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8128

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US20180247933A1

公开(公告)日：2018-08-30

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

CPC classification number: H01L27/0605 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76895 ,  H01L21/8252 ,  H01L23/5227 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/535 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/737 ,  H01L29/7786 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuity may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.

公开(公告)号：US20180211897A1

公开(公告)日：2018-07-26

申请号：US15597386

申请日：2017-05-17

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI

IPC: H01L23/367 ,  H01L29/737 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L23/3677 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.