公开(公告)号：US10069474B2

公开(公告)日：2018-09-04

申请号：US15137662

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy ,  Yunfei Ma ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H9/05 ,  H03H9/10 ,  H03H9/15 ,  H03H3/02 ,  H01F17/02 ,  H05K1/18 ,  H03H9/54 ,  H05K3/46 ,  H05K1/03 ,  H05K3/00 ,  H03H3/08 ,  H03H9/64 ,  H01F17/00 ,  H03H7/01 ,  H03H7/46

Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.

公开(公告)号：US10026546B2

公开(公告)日：2018-07-17

申请号：US15160776

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  David Francis Berdy

IPC: H03H7/46 ,  H01F27/40 ,  H01F27/28 ,  H01F27/29 ,  H01F41/02 ,  H03H7/01

Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.

公开(公告)号：US09692386B2

公开(公告)日：2017-06-27

申请号：US14177620

申请日：2014-02-11

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun

IPC: H03H7/01 ,  H01F27/28 ,  H01L23/522

CPC classification number: H03H7/0115 ,  H01F27/2866 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48464 ,  Y10T29/417 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.

公开(公告)号：US09502586B1

公开(公告)日：2016-11-22

申请号：US14853931

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01L29/93 ,  H01L27/108 ,  H01L21/70 ,  H01L27/08 ,  H01L29/66

CPC classification number: H01L27/0808 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/78 ,  H01L27/1203 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/93

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Abstract translation: 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极，作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外，掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。

公开(公告)号：US09468098B2

公开(公告)日：2016-10-11

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H01L23/48 ,  H01L23/64 ,  H05K1/02 ,  H05K3/36 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。

公开(公告)号：US09384883B2

公开(公告)日：2016-07-05

申请号：US14155172

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun

IPC: H01F27/28 ,  H01F41/00 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F27/2804 ,  H01F41/00 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract translation: 3D嵌套变压器包括具有与一组迹线菊花链连接的一组通过衬底通孔的衬底。 至少一些直通衬底通孔具有第一和第二导电区域。 该组迹线还包括将至少一些贯穿衬底通孔的第一导电区域耦合在一起的第一组迹线，以及将至少一些第二导电区域连接在一起的穿过衬底通孔的第二组迹线。

公开(公告)号：US09343399B2

公开(公告)日：2016-05-17

申请号：US14149530

申请日：2014-01-07

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Niranjan Sunil Mudakatte

IPC: H01L21/02 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L27/01 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L23/49822 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract translation: 集成电路器件包括衬底，以及在衬底上的包括第一导电层和第二导电层的第一层间电介质层。 集成电路器件还包括第一导电叠层，其包括用第一通孔耦合到第二导电层的一部分的第三导电层。 集成电路器件还包括第二导电叠层，其包括直接位于与衬底隔离的第三导电层的一部分上的第四导电层。 集成电路器件还包括围绕第三导电层和第四导电层的第二层间介质层。

公开(公告)号：US09335384B2

公开(公告)日：2016-05-10

申请号：US14037142

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R33/02 ,  G01R29/08

CPC classification number: G01R33/02 ,  G01R29/0814

Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

Abstract translation: 一种用于测试电子设备的近场磁场的方法和装置。 该方法包括使用在第一方向上定向的环形天线来测量磁场。 在测量磁场的同时，将环形天线扫过所需的方位角范围。 一旦第一方向测试完成，环形天线就变成第二定位方向。 然后在第二取向方向上测量磁场，并且扫过第二方向上所需的取向角范围。 该装置提供连接到同轴探针的环形天线，同轴电缆用作中心导体和两个外部导体。 轴安装在环形天线上，并连接到步进电机。 还提供用于移动臂组件的伺服电动机。

公开(公告)号：US20160064391A1

公开(公告)日：2016-03-03

申请号：US14469341

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Woo Tag Kang ,  Changhan Hobie Yun ,  Wei-Chuan Chen

IPC: H01L27/115 ,  G11C11/409 ,  G11C11/22 ,  H01L27/108

CPC classification number: H01L27/11507 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/409 ,  H01G7/06 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10897 ,  H01L27/11512 ,  H01L27/11514 ,  H01L28/91

Abstract: A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material.

Abstract translation: 存储单元包括包括第一金属层和第二金属层的电容器。 电容器包括设置在第一金属层和第二金属层之间的铁电层。 铁电层是单层双稳态不对称结晶材料。

公开(公告)号：US20150311275A1

公开(公告)日：2015-10-29

申请号：US14791164

申请日：2015-07-02

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/012 ,  H01G4/30 ,  H01G4/12 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.