公开(公告)号：US20170040225A1

公开(公告)日：2017-02-09

申请号：US15298933

申请日：2016-10-20

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

摘要翻译： 制造使用碳掺杂硅层的场效应晶体管的方法，用于基本上减少形成在基本上未掺杂的沟道层下面的掺杂屏蔽层的扩散，包括形成原位外延碳掺杂的硅衬底，其被掺杂以形成屏蔽层 碳掺杂硅衬底并且在碳掺杂硅衬底上形成基本上未掺杂的硅层。 该方法可以包括在筛网层下方注入碳并在筛网层上方形成薄层原位外延碳掺杂硅。 屏幕层可以形成在硅衬底层或碳掺杂硅衬底中。

公开(公告)号：US20170012044A1

公开(公告)日：2017-01-12

申请号：US15272113

申请日：2016-09-21

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson ,  Sachin R. Sonkusale ,  Weimin Zhang

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/7833

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an anaolog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的σVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括具有外延沟道层的anaolog器件和数字器件，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。

公开(公告)号：US09508800B2

公开(公告)日：2016-11-29

申请号：US14977887

申请日：2015-12-22

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC分类号： H01L29/10 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

公开(公告)号：US20160268133A1

公开(公告)日：2016-09-15

申请号：US14600865

申请日：2015-01-20

申请人： MIE Fujitsu Semiconductor Limited

发明人： Lance S. Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/04 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/10

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

摘要翻译： 制造使用碳掺杂硅层的场效应晶体管的方法，用于基本上减少形成在基本上未掺杂的沟道层下面的掺杂屏蔽层的扩散，包括形成原位外延碳掺杂的硅衬底，其被掺杂以形成屏蔽层 碳掺杂硅衬底并且在碳掺杂硅衬底上形成基本上未掺杂的硅层。 该方法可以包括在筛网层下方注入碳并在筛网层上方形成薄层原位外延碳掺杂硅。 屏幕层可以形成在硅衬底层或碳掺杂硅衬底中。

公开(公告)号：US10014387B2

公开(公告)日：2018-07-03

申请号：US15047052

申请日：2016-02-18

申请人： Mie Fujitsu Semiconductor Limited

发明人： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

摘要： A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

公开(公告)号：US09922977B2

公开(公告)日：2018-03-20

申请号：US15192288

申请日：2016-06-24

申请人： Mie Fujitsu Semiconductor Limited

发明人： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

IPC分类号： H01L29/10 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7836

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.

公开(公告)号：US09865596B2

公开(公告)日：2018-01-09

申请号：US15272113

申请日：2016-09-21

申请人： Mie Fujitsu Semiconductor Limited

发明人： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson ,  Sachin R. Sonkusale ,  Weimin Zhang

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/7833

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

公开(公告)号：US09812550B2

公开(公告)日：2017-11-07

申请号：US15419315

申请日：2017-01-30

申请人： Mie Fujitsu Semiconductor Limited

发明人： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

摘要： A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

公开(公告)号：US09786703B2

公开(公告)日：2017-10-10

申请号：US15285308

申请日：2016-10-04

申请人： Mie Fujitsu Semiconductor Limited

发明人： Teymur Bakhishev ,  Lingquan Wang ,  Dalong Zhao ,  Pushkar Ranade ,  Scott E. Thompson

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/146 ,  H01L29/78 ,  H01L29/10 ,  H04N5/3745

CPC分类号： H01L27/14616 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7833 ,  H01L29/7838 ,  H04N5/3745

摘要： Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

公开(公告)号：US09514940B2

公开(公告)日：2016-12-06

申请号：US14600865

申请日：2015-01-20

申请人： MIE Fujitsu Semiconductor Limited

发明人： Lance S. Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/425 ,  H01L21/04 ,  H01L21/265 ,  H01L21/82 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.