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    METHOD AND APPARATUS FOR DATA TRANSFER
    31.
    发明申请
    METHOD AND APPARATUS FOR DATA TRANSFER 有权
    数据传输的方法和装置

    公开(公告)号：US20070028029A1

    公开(公告)日：2007-02-01

    申请号：US11161369

    申请日：2005-08-01

    申请人： Stephen Morein ,  Robert Bloemer

    发明人： Stephen Morein ,  Robert Bloemer

    IPC分类号： G06F12/00 ,  G11C7/10

    CPC分类号： G06F13/1615 ,  G06F13/1684 ,  G11C7/1072

    摘要： A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

    摘要翻译： 一种用于数据传输的方法和装置包括跨越第一双向总线接收第一数据分组并且跨越第二双向总线接收第二数据分组。 接下来，将第一数据分组写入可操作地耦合到第一双向总线和第二双向总线的第一寄存器。 第二数据分组被写入可操作地耦合到第一双向总线和第二双向总线的第二寄存器。 然后，第二数据分组在第一双向总线上传输，并且第一数据分组跨第二个双向总线传输，从而提供跨多个双向总线的数据传输，并提供跨数据传输的数据 要存储在中间寄存器中的总线，以便可以在下一个时钟周期中传输数据，克服任何延迟要求。

    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
    32.
    发明授权
    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
    使用专用接口线路的高速非对称接口中的错误检测

    公开(公告)号：US08892963B2

    公开(公告)日：2014-11-18

    申请号：US11595619

    申请日：2006-11-09

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/08

    CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

    Error detection in high-speed asymmetric interfaces
    35.
    发明授权
    Error detection in high-speed asymmetric interfaces 有权
    高速非对称接口中的错误检测

    公开(公告)号：US07996731B2

    公开(公告)日：2011-08-09

    申请号：US11592074

    申请日：2006-11-01

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

    Internal BUS Bridge Architecture and Method in Multi-Processor Systems
    36.
    发明申请
    Internal BUS Bridge Architecture and Method in Multi-Processor Systems 有权
    多处理器系统中的内部总线桥结构和方法

    公开(公告)号：US20100088452A1

    公开(公告)日：2010-04-08

    申请号：US12245686

    申请日：2008-10-03

    申请人： Stephen Morein ,  Mark S. Grossman

    发明人： Stephen Morein ,  Mark S. Grossman

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4027 ,  G06F13/4031 ,  G06F13/4068

    摘要： An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

    摘要翻译： 描述了内部总线桥结构和方法。 实施例包括具有通过至少一个总线端点内部的主机总线桥耦合到总线根的多个总线端点的系统。 此外，总线端点彼此直接耦合。 实施例可用于已知的总线协议。

    Peer-To-Peer Special Purpose Processor Architecture and Method
    37.
    发明申请
    Peer-To-Peer Special Purpose Processor Architecture and Method 有权
    对等专用处理器架构与方法

    公开(公告)号：US20090248941A1

    公开(公告)日：2009-10-01

    申请号：US12184197

    申请日：2008-07-31

    申请人： Stephen Morein ,  Mark S. Grossman ,  Warren Fritz Kruger ,  Brian Etscheid

    发明人： Stephen Morein ,  Mark S. Grossman ,  Warren Fritz Kruger ,  Brian Etscheid

    IPC分类号： G06F13/28 ,  G06F13/20

    CPC分类号： G06F13/4265 ,  G06F13/4004 ,  G06F2213/0026

    摘要： A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

    摘要翻译： 描述了一种对等专用处理器架构和方法。 实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到多个专用处理器中的至少一个的直接总线和耦合到存储器控制器的存储器控​​制器 至多个专用处理器，其中至少一个存储器控制器确定是经由主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线接收数据。

    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
    38.
    发明申请
    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
    使用专用接口线路的高速非对称接口中的错误检测

    公开(公告)号：US20070104327A1

    公开(公告)日：2007-05-10

    申请号：US11595619

    申请日：2006-11-09

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    IPC分类号： H04N7/167

    CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

    Asymmetrical IO method and system
    39.
    发明申请
    Asymmetrical IO method and system 有权
    非对称IO方法和系统

    公开(公告)号：US20070067660A1

    公开(公告)日：2007-03-22

    申请号：US11231078

    申请日：2005-09-19

    申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    IPC分类号： G06F1/12

    CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

    摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

    摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

    Method and apparatus for generating compressed stencil test information
    40.
    发明申请
    Method and apparatus for generating compressed stencil test information 有权

    公开(公告)号：US20060033743A1

    公开(公告)日：2006-02-16

    申请号：US10917268

    申请日：2004-08-11

    申请人： Stephen Morein

    发明人： Stephen Morein

    IPC分类号： G06T1/00 ,  G06F15/00

    CPC分类号： G06T15/005

    摘要： A method for rendering pixels for display includes generating stencil values on a per pixel basis for storage in stencil buffer memory; selecting a group of stencil values that represent a block of pixels; generating compressed stencil data associated with the group of stencil values; and performing stencil testing on a corresponding incoming block of pixels using the compressed stencil data.