IMAGING OVERLAY TARGETS USING MOIRÉ ELEMENTS AND ROTATIONAL SYMMETRY ARRANGEMENTS

    公开(公告)号:US20250021019A1

    公开(公告)日:2025-01-16

    申请号:US18902197

    申请日:2024-09-30

    Abstract: A metrology target may include a first rotationally symmetric working zone with one or more instances of a first pattern and a second rotationally-symmetric working zone with one or more instances of a second pattern, where at least one of the first pattern or the second pattern is a Moiré pattern formed from a first grating structure with a first pitch along a measurement direction on a first sample layer and a second grating structure with a second pitch different than the first pitch along the measurement direction on a second sample layer. Centers of rotational symmetry of the first and second working zones may overlap by design when an overlay error between the first sample layer and the second layer is zero. A difference between the centers of rotational symmetry of the first and second working zones may indicate an overlay error between the first and second sample layers.

    Verification metrology targets and their design

    公开(公告)号:US11874605B2

    公开(公告)日:2024-01-16

    申请号:US16921880

    申请日:2020-07-06

    CPC classification number: G03F7/70491 G03F7/70616 G06F30/00 H01L22/30

    Abstract: Metrology target design methods and verification targets are provided. Methods comprise using OCD data related to designed metrology target(s) as an estimation of a discrepancy between a target model and a corresponding actual target on a wafer, and adjusting a metrology target design model to compensate for the estimated discrepancy. The dedicated verification targets may comprise overlay target features and be size optimized to be measureable by an OCD sensor, to enable compensation for inaccuracies resulting from production process variation. Methods also comprise modifications to workflows between manufacturers and metrology vendors which provide enable higher fidelity metrology target design models and ultimately higher accuracy of metrology measurements.

    OVERLAY MARK DESIGN FOR ELECTRON BEAM OVERLAY

    公开(公告)号:US20230324810A1

    公开(公告)日:2023-10-12

    申请号:US18204662

    申请日:2023-06-01

    CPC classification number: G03F7/70633 G03F7/70683

    Abstract: Electron beam overlay targets and method of performing overlay measurements on a target using a semiconductor metrology tool are provided. One target includes a plurality of electron beam overlay elements and a plurality of two-dimensional elements that provide at least one two-dimensional imaging. The plurality of two dimensional elements are an array of evenly-spaced polygonal gratings across at least three rows and at least three columns. Another target includes a plurality of electron beam overlay elements and a plurality of AIMid elements. Each of the electron beam overlay elements includes at least two gratings that are overlaid at a perpendicular orientation to each other. The plurality of AIMid elements includes at least two gratings that are overlaid at a perpendicular orientation to each other.

    Induced displacements for improved overlay error metrology

    公开(公告)号:US11774863B2

    公开(公告)日:2023-10-03

    申请号:US17612907

    申请日:2021-10-21

    CPC classification number: G03F7/70633 G03F7/70525

    Abstract: A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to define a plurality of overlay targets comprising first target features formed in the first film layer having respective first locations, which are spaced apart by first nominal distances, and second target features formed in the second film layer having respective second locations, which are spaced apart by second nominal distances, which are different from the first nominal distances. An image of the semiconductor substrate is processed to measure respective displacements between the first and second target locations in each of the overlay targets, and to estimate both an actual overlay error between the patterning of the first and second film layers and a measurement error of the imaging assembly.

    Induced Displacements for Improved Overlay Error Metrology

    公开(公告)号:US20230129618A1

    公开(公告)日:2023-04-27

    申请号:US17612907

    申请日:2021-10-21

    Abstract: A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to define a plurality of overlay targets comprising first target features formed in the first film layer having respective first locations, which are spaced apart by first nominal distances, and second target features formed in the second film layer having respective second locations, which are spaced apart by second nominal distances, which are different from the first nominal distances. An image of the semiconductor substrate is processed to measure respective displacements between the first and second target locations in each of the overlay targets, and to estimate both an actual overlay error between the patterning of the first and second film layers and a measurement error of the imaging assembly.

    Single cell in-die metrology targets and measurement methods

    公开(公告)号:US11476144B2

    公开(公告)日:2022-10-18

    申请号:US16609873

    申请日:2019-09-30

    Inventor: Mark Ghinovker

    Abstract: Metrology targets and methods are provided, which comprise at least two overlapping structures configured to be measurable in a mutually exclusive manner at least at two different corresponding optical conditions. The targets may be single cell targets which are measured at different optical conditions which enable independent measurements of the different layers of the target. Accordingly, the targets may be designed to be very small, and be located in-die for providing accurate metrology measured of complex devices.

    Misregistration Target Having Device-Scaled Features Useful in Measuring Misregistration of Semiconductor Devices

    公开(公告)号:US20220013468A1

    公开(公告)日:2022-01-13

    申请号:US16964714

    申请日:2020-06-25

    Abstract: A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.

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