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    MECHANICAL PUNCHED VIA FORMATION IN ELECTRONICS PACKAGE AND ELECTRONICS PACKAGE FORMED THEREBY
    37.
    发明申请
    MECHANICAL PUNCHED VIA FORMATION IN ELECTRONICS PACKAGE AND ELECTRONICS PACKAGE FORMED THEREBY 有权

    公开(公告)号：US20210375813A1

    公开(公告)日：2021-12-02

    申请号：US15929925

    申请日：2020-05-29

    Applicant: General Electric Company

    Inventor： Christopher James Kapusta ,  Youichi Nishihara

    IPC: H01L23/00

    Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.

    Sensor system and method
    38.
    发明授权
    Sensor system and method 有权

    公开(公告)号：US11079359B2

    公开(公告)日：2021-08-03

    申请号：US16720471

    申请日：2019-12-19

    Applicant: General Electric Company

    Inventor： Joseph Alfred Iannotti ,  Christopher James Kapusta ,  David Richard Esler

    IPC: G01N29/22 ,  G01K11/26 ,  G01N29/24 ,  G01D11/24

    Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.

    Electronics package for light emitting semiconductor devices and method of manufacturing thereof
    39.
    发明授权
    Electronics package for light emitting semiconductor devices and method of manufacturing thereof 有权

    公开(公告)号：US10957832B2

    公开(公告)日：2021-03-23

    申请号：US16166313

    申请日：2018-10-22

    Applicant: General Electric Company

    Inventor： Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

    IPC: H01L33/62 ,  H01L23/538 ,  H01L33/54 ,  H01L33/60 ,  H01L25/075 ,  H01L25/16 ,  H01L33/64

    Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.

    SYSTEMS AND METHODS FOR SAW WAFER LEVEL ASSEMBLY WITH TOP SIDE CONTACTS
    40.
    发明申请
    SYSTEMS AND METHODS FOR SAW WAFER LEVEL ASSEMBLY WITH TOP SIDE CONTACTS 有权

    公开(公告)号：US20210013866A1

    公开(公告)日：2021-01-14

    申请号：US16509554

    申请日：2019-07-12

    Applicant: General Electric Company

    Inventor： Joseph Alfred Iannotti ,  Christopher James Kapusta

    IPC: H03H9/10 ,  H03H9/05 ,  H03H3/08

    Abstract: A wafer level assembly is disclosed. The wafer level assembly includes a device wafer, and a plurality of electrodes disposed on the device wafer, wherein the device wafer the plurality of electrodes form a surface acoustic wave (SAW) device, a plurality of device pads disposed on the device wafer, wherein each of the plurality of electrodes are coupled to one of the device pads, a cap wafer coupled to the device wafer through a seal layer, the cap wafer having a plurality of contact pads and a plurality of interconnect pads integral with a surface of the cap wafer, wherein each of the plurality of contact pads is coupled to one of the plurality of interconnect pads, and a plurality of conductive interconnects, wherein each of the plurality of conductive interconnects is coupled between one of the plurality of device pads and one of the plurality of interconnect pads.

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