公开(公告)号：US20250031300A1

公开(公告)日：2025-01-23

申请号：US18451477

申请日：2023-08-17

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Amendra Koul ,  David Nozadze ,  Joel Richard Goergen ,  Upen Reddy Kareti ,  Sayed Ashraf Mamun

IPC: H05K1/02

Abstract: Provide for herein is an apparatus that includes multiple printed circuit board (PCB) layers and a via assembly. The via assembly includes a signal via extending through the multiple layers, and the signal via is configured to transmit a signal between the layers. The via assembly also includes a capacitive structure connected to the signal via to adjust an impedance of the via assembly along the via assembly. The capacitive structure is physically and electrically separate from other components of the PCB.

公开(公告)号：US20250029931A1

公开(公告)日：2025-01-23

申请号：US18453720

申请日：2023-08-22

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Amendra Koul ,  David Nozadze ,  Joel Richard Goergen ,  Sayed Ashraf Mamun ,  Srinath Penugonda

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

Abstract: In some embodiments, an integrated circuit (IC) includes multiple packages that are separate from one another. Each package includes a pad, and a core via is electrically coupled to the pads of the separate packages to electrically couple the packages to one another. At least one of the pads includes an oblong shape to match its impedance with the impedance of the core via.

公开(公告)号：US20240356251A1

公开(公告)日：2024-10-24

申请号：US18455803

申请日：2023-08-25

Applicant: Cisco Technology, Inc.

Inventor： David Nozadze ,  Mike Sapozhnikov ,  Amendra Koul ,  Sayed Ashraf Mamun ,  Upen Reddy Kareti

IPC: H01R12/53 ,  H01R12/55 ,  H05K1/14

CPC classification number: H01R12/53 ,  H01R12/55 ,  H05K1/144 ,  H01R43/007 ,  H05K1/0219 ,  H05K2201/0314 ,  H05K2201/041 ,  H05K2201/10356

Abstract: In some aspects, the techniques described herein relate to an apparatus for connecting cables to Input Output (IO) connector pins, including: a first Printed Circuit Board (PCB) configured to receive terminal ends of a plurality of cables, wherein the terminal ends of the plurality of cables are electrically isolated from one another in the first PCB; a second PCB configured to receive a plurality of IO connector pins, wherein the plurality of IO connector pins are electrically isolated from one another in the second PCB; and wherein the first PCB is configured to join to the second PCB to connect each of the terminal ends of the plurality of cables to corresponding pins of the plurality of IO connector pins.

公开(公告)号：US11781858B2

公开(公告)日：2023-10-10

申请号：US17573219

申请日：2022-01-11

Applicant: Cisco Technology, Inc.

Inventor： Amendra Koul ,  Yaochao Yang ,  Mike Sapozhnikov ,  Joel Richard Goergen ,  Kartheek Nalla

IPC: G01B11/24 ,  G01N21/956 ,  G01B11/26 ,  H05K3/00

CPC classification number: G01B11/24 ,  G01B11/26 ,  G01N21/956 ,  H05K3/00 ,  G01N2021/95638

Abstract: A method is provided that includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.

公开(公告)号：US11706870B2

公开(公告)日：2023-07-18

申请号：US17503690

申请日：2021-10-18

Applicant: Cisco Technology, Inc.

Inventor： Joel Goergen ,  Jessica Kiefer ,  Alpesh Umakant Bhobe ,  Kameron Rose Hurst ,  D. Brice Achkir ,  Amendra Koul ,  Scott Hinaga ,  David Nozadze

IPC: H05K3/46 ,  H05K1/09

CPC classification number: H05K1/09 ,  H05K3/4644 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2203/1545

Abstract: A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.

公开(公告)号：US11293752B2

公开(公告)日：2022-04-05

申请号：US16868383

申请日：2020-05-06

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Amendra Koul ,  Yaochao Yang ,  Mike Sapozhnikov ,  Joel Richard Goergen ,  Kartheek Nalla

IPC: G01B11/24 ,  G01N21/956 ,  G01B11/26 ,  H05K3/00

Abstract: In one embodiment, a method includes inspecting a fiber weave for use in a printed circuit board with an automated optical inspection tool and identifying a distance between fiber bundles in the fiber weave. The fiber weave comprises a plurality of the fiber bundles woven to form the fiber weave and a portion of the fiber bundles comprise markers and identifying a distance between the fiber bundles in the fiber weave comprises measuring a distance between the markers.

公开(公告)号：US20210337666A1

公开(公告)日：2021-10-28

申请号：US17006016

申请日：2020-08-28

Applicant: Cisco Technology, Inc.

Inventor： Joel Goergen ,  Jessica Kiefer ,  Alpesh Umakant Bhobe ,  Kameron Rose Hurst ,  D. Brice Achkir ,  Amendra Koul ,  Scott Hinaga ,  David Nozadze

IPC: H05K1/09 ,  H05K3/46

Abstract: A power plane structure for a printed circuit board includes a copper layer, and a carbon layer applied directly to a surface of the copper layer. The carbon layer can include graphite or graphene. In additional embodiments, a duplicate power plane structure for a printed circuit board includes two power planes separated by an insulating core, each power plane including a copper layer and a carbon layer applied directly to a surface of the copper layer.

公开(公告)号：US10674598B1

公开(公告)日：2020-06-02

申请号：US16596623

申请日：2019-10-08

Applicant: CISCO TECHNOLOGY, INC.

Inventor： David Nozadze ,  Amendra Koul ,  Joel Richard Goergen ,  Mike Sapozhnikov

IPC: H05K1/02 ,  H05K1/11 ,  H01P3/08 ,  H05K3/40 ,  H01P11/00 ,  H01P7/08 ,  H05K3/00

Abstract: In one embodiment, an apparatus includes a printed circuit board, a via-stub resonator formed in the printed circuit board, a plurality of vias surrounding the via-stub resonator, and a microstrip connected to the via-stub resonator for use in measuring an insertion loss to provide a resonance frequency. The via-stub resonator is designed to reproduce a dielectric constant value of a known material in a simulation. A via dielectric constant in an x and y plane is calculated based on the resonance frequency. A method for measuring the via dielectric constant using the via-stub resonator is also disclosed herein.