CHANNEL PREDICTIVE BEHAVIOR AND FAULT ANALYSIS

    公开(公告)号:US20230198639A1

    公开(公告)日:2023-06-22

    申请号:US18172430

    申请日:2023-02-22

    CPC classification number: H04B17/15 H04B17/24 H04B10/071

    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.

    Channel predictive behavior and fault analysis

    公开(公告)号:US11606152B2

    公开(公告)日:2023-03-14

    申请号:US17342316

    申请日:2021-06-08

    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.

    POWER METHOD FOR HIGHER CURRENT ASIC POWER DELIVERY

    公开(公告)号:US20250151198A1

    公开(公告)日:2025-05-08

    申请号:US18434943

    申请日:2024-02-07

    Abstract: Techniques to move high current power distribution layers for integrated circuit core power and serializer-deserializer (SERDES) power into a center area of the integrated circuit footprint. This provides a more reliable and higher current distribution into the center of a large integrated circuit footprint, without causing disruption of high speed signal routing or increased signal integrity burden to the high speed signals. Arrangements and methods for routing out the core power area of a main printed circuit board under an integrated circuit and replacing it with a custom power printed circuit board (power plug) that is attached by a metalized paste sintering process. This provides a more reliable and higher current distribution into the center of a large integrated circuit or other high-power component, without causing disruption of high speed signal routing.

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