公开(公告)号：US06756282B2

公开(公告)日：2004-06-29

申请号：US10164409

申请日：2002-06-10

Applicant: Yoshihisa Nagano ,  Yasuhiro Uemoto

Inventor： Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC: H01L2120

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract translation: 保护绝缘膜沉积在形成在半导体衬底上的第一和第二场效应晶体管上。 在保护绝缘膜上形成由电容器下电极构成的电容器，由绝缘金属氧化物膜构成的电容绝缘膜和电容器上电极。 形成在保护绝缘膜中的第一接触插塞提供电容器下电极和第一场效应晶体管的杂质扩散层之间的直接连接。 形成在保护绝缘膜中的第二接触插塞提供电容器上电极和第二场效应晶体管的杂质扩散层之间的直接连接。

公开(公告)号：US06320214B1

公开(公告)日：2001-11-20

申请号：US09209214

申请日：1998-12-11

Applicant: Akihiro Matsuda ,  Yoshihisa Nagano ,  Yasuhiro Uemoto

Inventor： Akihiro Matsuda ,  Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC: H01L2976

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.

Abstract translation: 本发明提供一种包括半导体元件和与半导体元件相邻的虚设半导体元件的半导体器件。 当半导体元件是包括底部电极，顶部电极和电极之间的电介质层的电容器元件时，虚拟电容器元件在虚拟电极之间也具有虚拟电极和虚设电介质层。 虚拟电极被定位成使得电容器元件的顶部电极和虚拟顶部电极之间的空间处于预定范围（例如，0.3μm至14μm）。 由于在干蚀刻工艺中蚀刻离子与电容器电介质层的碰撞被抑制，因此虚拟电容器元件防止电容器介电层降解。

公开(公告)号：US06174822B1

公开(公告)日：2001-01-16

申请号：US09175250

申请日：1998-10-20

Applicant: Yoshihisa Nagano ,  Toshie Kutsunai ,  Yuji Judai ,  Yasuhiro Uemoto ,  Eiji Fujii

Inventor： Yoshihisa Nagano ,  Toshie Kutsunai ,  Yuji Judai ,  Yasuhiro Uemoto ,  Eiji Fujii

IPC: H01L2131

CPC classification number: H01L27/1085 ,  H01L21/76895 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract translation: 半导体器件包括：设置在其上具有集成电路的支撑衬底上并包括下电极，电介质膜和上电极的电容器; 设置为覆盖电容器的第一层间绝缘膜; 选择性地设置在所述第一层间绝缘膜上并通过形成在所述第一层间绝缘膜中的第一接触孔与所述集成电路和所述电容器电连接的第一互连; 由臭氧TEOS形成的第二层间绝缘膜，并设置为覆盖第一互连; 选择性地设置在第二层间绝缘膜上并通过形成在第二层间绝缘膜中的第二接触孔电连接到第一互连的第二互连; 以及设置成覆盖第二互连的钝化层。

公开(公告)号：US6166424A

公开(公告)日：2000-12-26

申请号：US109032

申请日：1998-07-02

Applicant: Takumi Mikawa ,  Yuji Judai ,  Yoshihisa Nagano

Inventor： Takumi Mikawa ,  Yuji Judai ,  Yoshihisa Nagano

IPC: H01L21/02 ,  H01L29/41

CPC classification number: H01L28/55 ,  H01L28/60 ,  Y10S438/957

Abstract: On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.

Abstract translation: 在基板上，设置有被填充在形成在钝化绝缘膜中的第二孔（电容确定孔）中的下电极，电容绝缘膜，钝化绝缘膜和上电极的第一部分膜。 下电极，电容绝缘膜和第一部分膜构成电容元件。 上电极具有与电容绝缘膜接触的第一部分膜和不与电容绝缘膜接触的第二部分膜。 由于由钛构成的下层膜和由铝合金膜构成的上层膜构成的第2电极线与上部电极的第1部分膜不同的第2部分膜接触，钛等 可以防止从第二电极线的侵入扩散到电容绝缘膜。

公开(公告)号：US06143597A

公开(公告)日：2000-11-07

申请号：US678866

申请日：1996-07-12

Applicant: Akihiro Matsuda ,  Yoshihisa Nagano ,  Toru Nasu ,  Koji Arita ,  Yasuhiro Uemoto

Inventor： Akihiro Matsuda ,  Yoshihisa Nagano ,  Toru Nasu ,  Koji Arita ,  Yasuhiro Uemoto

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/108

CPC classification number: H01L28/56

Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.

Abstract translation: 一种制造电容器的方法包括在第一电极上形成由铁电材料或具有高介电常数的介电材料构成的第一介电层的步骤，烧结第一介电层的步骤，形成第二介电层的步骤 第一电介质层，以及在第二电介质层上形成第二电极的步骤。 通过在具有大晶粒尺寸的第一电介质层上形成具有小晶粒尺寸的第二电介质层，电容器绝缘层的表面变平。

公开(公告)号：US5652171A

公开(公告)日：1997-07-29

申请号：US594945

申请日：1996-01-31

Applicant: Yoshihisa Nagano ,  Eiji Fujii

Inventor： Yoshihisa Nagano ,  Eiji Fujii

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L21/02071 ,  H01L21/32136 ,  H01L28/60 ,  H01L28/65

Abstract: A platinum bottom electrode film, a dielectric film composed of a high permittivity dielectric material or a ferroelectric material, and a platinum top electrode film are formed on a substrate on which circuit elements and wiring are formed, and the platinum top electrode film and the dielectric film are selectively dry-etched by using etching gas containing chlorine, then plasma generated by discharging gas containing fluorine is irradiated. By this method of manufacturing a semiconductor device including a capacitor, there is almost no residual chlorine, and hence erosion of the dielectric film by residual chlorine is prevented.

Abstract translation: 在其上形成有电路元件和布线的基板上形成铂底部电极膜，由介电常数高的电介质材料或铁电体材料构成的电介质膜和铂电极膜，并且铂顶部电极膜和电介质 通过使用含有氯的蚀刻气体选择性地干蚀刻膜，然后照射通过排出含氟气体产生的等离子体。 通过这种制造包括电容器的半导体器件的方法，几乎​​没有残留的氯，因此防止了由残留氯引起的电介质膜的腐蚀。

公开(公告)号：US5527729A

公开(公告)日：1996-06-18

申请号：US412563

申请日：1995-03-29

Applicant: Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

Inventor： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/40

Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

Abstract translation: 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

公开(公告)号：US5430671A

公开(公告)日：1995-07-04

申请号：US224589

申请日：1994-04-07

Applicant: Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

Inventor： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A semiconductor memory device comprising bit line, word line, plate electrode, ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line, and adjusting capacitor for adjusting bit line capacitance coupled to said bit line. The adjusting capacitor is provided to increase the potential difference for reading and control occurrence of operating errors.

Abstract translation: 一种半导体存储器件，包括位线，字线，平板电极，具有第一电极和第二电极的铁电电容器，所述第二电极耦合到所述平板电极，MOS晶体管的源极耦合到所述第一电极，栅极耦合 到所述字线，并且所述漏极耦合到所述位线，以及调整电容器，用于调整耦合到所述位线的位线电容。 提供调整电容器以增加用于读取和控制操作错误发生的电位差。

公开(公告)号：US07053436B2

公开(公告)日：2006-05-30

申请号：US10752668

申请日：2004-01-08

Applicant: Yoshihisa Nagano ,  Toshie Kutsunai

Inventor： Yoshihisa Nagano ,  Toshie Kutsunai

IPC: H01L27/108

CPC classification number: H01L28/55 ,  H01L21/7687 ,  H01L27/10852 ,  H01L28/65

Abstract: A conductive oxygen barrier layer is formed on an interlayer dielectric film and patterned such that it is in contact with the top surface of a contact plug to prevent the diffusion of oxygen into the contact plug from above. The conductive oxygen barrier layer is composed of a lower layer containing a conductive nitride such as TiAlN, and an upper layer containing a conductive oxide such as IrO2. An insulative oxygen barrier layer composed of Al2O3 and having a thickness of approximately 20 nm is formed on the side surfaces of the conductive oxygen barrier layer to prevent the diffusion of oxygen into the contact plug from the sides, such as from the sides of the lower layer of the conductive barrier layer.

Abstract translation: 导电氧阻隔层形成在层间电介质膜上并被图案化，使得其与接触插塞的顶表面接触以防止氧气从上方扩散到接触塞中。 导电氧阻隔层由包含诸如TiAlN的导电氮化物的下层和包含诸如IrO 2的导电氧化物的上层组成。 在导电氧阻隔层的侧表面上形成厚度约为20nm的由Al 2 O 3 3 N 2构成的绝缘性氧阻隔层，以防止扩散 氧从侧面进入接触塞，例如从导电阻挡层的下层的侧面。

公开(公告)号：US06939725B2

公开(公告)日：2005-09-06

申请号：US10769808

申请日：2004-02-03

Applicant: Toshie Kutsunai ,  Shinichiro Hayashi ,  Yuji Judai ,  Yoshihisa Nagano

Inventor： Toshie Kutsunai ,  Shinichiro Hayashi ,  Yuji Judai ,  Yoshihisa Nagano

IPC: H01L23/522 ,  C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L21/00 ,  H01L29/76

CPC classification number: H01L28/55 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31612

Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.

Abstract translation: 在半导体衬底上形成包括电容器下电极，高电介质膜的电容器电介质膜或铁电体膜和电容器上电极的电容器。 在半导体衬底上形成保护膜以覆盖电容器。 具有相对较大含水量的第一TEOS膜通过臭氧浓度相对较低的第一TEOS-O 3 CVD形成在保护膜上。 通过第二TEOS-O 3 3在第一TEOS-O 3膜上形成具有相对较小含水量的第二TEOS-O 3膜。 臭氧浓度相对较高的CVD。