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    Method of manufacturing a capacitor having metal electrodes
    3.
    发明授权
    Method of manufacturing a capacitor having metal electrodes 失效
    制造具有金属电极的电容器的方法

    公开(公告)号：US5527729A

    公开(公告)日：1996-06-18

    申请号：US412563

    申请日：1995-03-29

    Applicant: Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    Inventor： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC classification number: H01L28/40

    Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

    Abstract translation: 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

    Semiconductor device and method for fabricating the same
    4.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06809000B2

    公开(公告)日：2004-10-26

    申请号：US09797987

    申请日：2001-03-05

    Applicant: Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    Inventor： Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    IPC: H01L2120

    CPC classification number: H01L28/55

    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

    Abstract translation: 本发明的半导体器件包括形成在基板上的电容器器件，其包括电容式下电极，由绝缘金属氧化物膜制成的电容绝缘膜和电容上电极。 在电容器装置上形成具有到达电容上电极的开口的层间绝缘膜。 在层间绝缘膜上形成包括钛膜的金属互连，以便通过开口与电容上电极电连接。 在电容上电极和金属互连之间形成具有导电性的防扩散膜，以防止构成金属互连的钛膜的钛原子通过电容上电极并扩散到电容绝缘膜。

    Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same
    5.
    发明授权
    Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same 失效
    具有改进的抗扩散性能的半导体电容器件及其制造方法

    公开(公告)号：US06239462B1

    公开(公告)日：2001-05-29

    申请号：US09120893

    申请日：1998-07-23

    Applicant: Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    Inventor： Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    IPC: H01L27108

    CPC classification number: H01L28/55

    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

    Abstract translation: 本发明的半导体器件包括形成在基板上的电容器器件，其包括电容式下电极，由绝缘金属氧化物膜制成的电容绝缘膜和电容上电极。 在电容器装置上形成具有到达电容上电极的开口的层间绝缘膜。 在层间绝缘膜上形成包括钛膜的金属互连，以便通过开口与电容上电极电连接。 在电容上电极和金属互连之间形成具有导电性的防扩散膜，以防止构成金属互连的钛膜的钛原子通过电容上电极并扩散到电容绝缘膜。

    Method of manufacturing semiconductor devices
    6.
    发明授权
    Method of manufacturing semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US5599424A

    公开(公告)日：1997-02-04

    申请号：US571732

    申请日：1995-12-13

    Applicant: Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    Inventor： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/00

    CPC classification number: H01L28/40

    Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

    Abstract translation: 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

    Semiconductor device and method for fabricating the same
    7.
    发明申请
    Semiconductor device and method for fabricating the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050045990A1

    公开(公告)日：2005-03-03

    申请号：US10950532

    申请日：2004-09-28

    Applicant: Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    Inventor： Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/00

    CPC classification number: H01L28/55

    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

    Abstract translation: 本发明的半导体器件包括形成在基板上的电容器器件，其包括电容式下电极，由绝缘金属氧化物膜制成的电容绝缘膜和电容上电极。 在电容器装置上形成具有到达电容上电极的开口的层间绝缘膜。 在层间绝缘膜上形成包括钛膜的金属互连，以便通过开口与电容上电极电连接。 在电容上电极和金属互连之间形成具有导电性的防扩散膜，以防止构成金属互连的钛膜的钛原子通过电容上电极并扩散到电容绝缘膜。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100264493A1

    公开(公告)日：2010-10-21

    申请号：US12731267

    申请日：2010-03-25

    Applicant: Yasufumi IZUTSU ,  Kazuyuki SAWADA ,  Yuji HARADA

    Inventor： Yasufumi IZUTSU ,  Kazuyuki SAWADA ,  Yuji HARADA

    IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/027 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

    Abstract: To provide a semiconductor device which includes a P-type Si substrate, an ESD protection element, and a protected element. The ESD protection element includes a source N-type diffusion region, and a high-concentration P-type diffusion region formed from under the source N-type diffusion region to at least under part of a gate electrode, covering the source N-type diffusion region within the P-type Si substrate, and having a higher P-type impurity concentration than the P-type Si substrate. The protected element includes a drain N-type diffusion region, and a low-concentration P-type diffusion region that is in contact with the drain N-type diffusion region within the P-type Si substrate. The drain electrode of the ESD protection element and the drain electrode of the protected element are connected, and the high-concentration P-type diffusion region 103 has a higher P-type impurity concentration than the low-concentration P-type diffusion region.

    Abstract translation: 提供一种包括P型Si衬底，ESD保护元件和受保护元件的半导体器件。 ESD保护元件包括源极N型扩散区域和从源极N型扩散区域至栅极电极的至少一部分形成的高浓度P型扩散区域，覆盖源极N型扩散区域 P型Si衬底内的P型杂质浓度高于P型Si衬底。 受保护元件包括漏极N型扩散区域和与P型Si衬底内的漏极N型扩散区域接触的低浓度P型扩散区域。 ESD保护元件的漏电极和受保护元件的漏电极连接，高浓度P型扩散区域103的P型杂质浓度比低浓度P型扩散区域高。

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