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    Mechanism for distributed-system-aware difference encoding/decoding in graph analytics
    31.
    发明授权
    Mechanism for distributed-system-aware difference encoding/decoding in graph analytics 有权

    公开(公告)号：US11068458B2

    公开(公告)日：2021-07-20

    申请号：US16202082

    申请日：2018-11-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert

    IPC: G06F16/22 ,  G06F16/901

    Abstract: A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the subject vertex via the edge. When the edge value is assigned to the first position, the edge value is determined by a first calculation, and when the edge value is assigned to position subsequent to the first position, the edge value is determined by a second calculation. In the computing node, the edge value is recorded in the edge array.

    CACHE LINE RE-REFERENCE INTERVAL PREDICTION USING PHYSICAL PAGE ADDRESS
    32.
    发明申请
    CACHE LINE RE-REFERENCE INTERVAL PREDICTION USING PHYSICAL PAGE ADDRESS 有权

    公开(公告)号：US20210182213A1

    公开(公告)日：2021-06-17

    申请号：US16716165

    申请日：2019-12-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jieming Yin ,  Yasuko Eckert ,  Subhash Sethumurugan

    IPC: G06F12/122

    Abstract: Systems, apparatuses, and methods for implementing cache line re-reference interval prediction using a physical page address are disclosed. When a cache line is accessed, a controller retrieves a re-reference interval counter value associated with the line. If the counter is less than a first threshold, then the address of the cache line is stored in a small re-use page buffer. If the counter is greater than a second threshold, then the address is stored in a large re-use page buffer. When a new cache line is inserted in the cache, if its address is stored in the small re-use page buffer, then the controller assigns a high priority to the line to cause it to remain in the cache to be re-used. If a match is found in the large re-use page buffer, then the controller assigns a low priority to the line to bias it towards eviction.

    Method and system for opportunistic load balancing in neural networks using metadata
    33.
    发明授权
    Method and system for opportunistic load balancing in neural networks using metadata 有权

    公开(公告)号：US10970120B2

    公开(公告)日：2021-04-06

    申请号：US16019374

    申请日：2018-06-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas Malaya ,  Yasuko Eckert

    IPC: G06F9/50 ,  G06N3/08

    Abstract: Methods and systems for opportunistic load balancing in deep neural networks (DNNs) using metadata. Representative computational costs are captured, obtained or determined for a given architectural, functional or computational aspect of a DNN system. The representative computational costs are implemented as metadata for the given architectural, functional or computational aspect of the DNN system. In an implementation, the computed computational cost is implemented as the metadata. A scheduler detects whether there are neurons in subsequent layers that are ready to execute. The scheduler uses the metadata and neuron availability to schedule and load balance across compute resources and available resources.

    Temperature-aware task scheduling and proactive power management
    35.
    发明授权
    Temperature-aware task scheduling and proactive power management 有权

    公开(公告)号：US10452437B2

    公开(公告)日：2019-10-22

    申请号：US15192784

    申请日：2016-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Abhinandan Majumdar ,  Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Yasuko Eckert

    IPC: G06F9/48 ,  G06F9/50 ,  G06F1/20 ,  G06F1/329

    Abstract: Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.

    Setting Operating Points for Circuits in an Integrated Circuit Chip
    37.
    发明申请
    Setting Operating Points for Circuits in an Integrated Circuit Chip 审中-公开

    公开(公告)号：US20190123648A1

    公开(公告)日：2019-04-25

    申请号：US16130136

    申请日：2018-09-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Huang ,  Yasuko Eckert ,  Xudong An ,  Muhammad Shoaib Bin Altaf ,  Jieming Yin

    IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46

    CPC classification number: H02M3/1582 ,  G05F1/468 ,  G05F1/56 ,  G05F1/575 ,  H02M2001/0022

    Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

    Dynamic and adaptive sleep state management
    38.
    发明授权
    Dynamic and adaptive sleep state management 有权

    公开(公告)号：US09921635B2

    公开(公告)日：2018-03-20

    申请号：US14068207

    申请日：2013-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora

    IPC: G06F1/32

    CPC classification number: G06F1/3228 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3231 ,  G06F1/324 ,  G06F1/3246 ,  Y02D10/126 ,  Y02D10/173

    Abstract: An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. In another example, the method includes determining whether an average idle time for a plurality of past idle events exceeds an energy break-even point threshold. If the average idle time for the plurality of past idle events exceeds the energy break-even point threshold, a device is immediately transitioned to a powered-down state upon receipt of a next idle event. If the average idle time for the plurality of past idle events does not exceed the energy break-even point threshold, transition of the device to the powered-down state is delayed.

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