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    SYSTEM FOR MANAGING MEMORY DEVICES
    31.
    发明申请
    SYSTEM FOR MANAGING MEMORY DEVICES 审中-公开

    公开(公告)号：US20180032281A1

    公开(公告)日：2018-02-01

    申请号：US15225343

    申请日：2016-08-01

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

    IPC: G06F3/06 ,  G11C11/406

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

    Memory subsystem calibration using substitute results
    35.
    发明授权
    Memory subsystem calibration using substitute results 有权

    公开(公告)号：US12293808B2

    公开(公告)日：2025-05-06

    申请号：US18455385

    申请日：2023-08-24

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

    IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    Voltage Ramp Memory Calibration
    36.
    发明申请
    Voltage Ramp Memory Calibration 有权

    公开(公告)号：US20250104790A1

    公开(公告)日：2025-03-27

    申请号：US18525088

    申请日：2023-11-30

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Jingkui Zheng ,  Srinivasa Rao Masanam

    IPC: G11C29/12 ,  G11C29/46

    Abstract: An apparatus for performing memory calibrations during a performance state change is disclosed. A memory controller is configured to convey a clock signal to a memory and includes a calibration control circuit configured to perform a plurality of calibrations of the clock signal during a change from a first one to a second one of a plurality of performance states, and a delay circuit configured to apply a delay to clock signal conveyed to the memory. In performing a one of the calibrations, the calibration control circuit is configured to convey, to the memory, a first command to begin a timing test that generates a count value indicative of a current voltage of the memory, receive the count value from the memory at a conclusion of the timing test, and cause the delay circuit to adjust, based on the count value, the delay applied to the clock signal.

    Memory Subsystem Calibration Using Substitute Results
    37.
    发明公开
    Memory Subsystem Calibration Using Substitute Results 审中-公开

    公开(公告)号：US20240062792A1

    公开(公告)日：2024-02-22

    申请号：US18455385

    申请日：2023-08-24

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

    IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    Memory subsystem calibration using substitute results
    38.
    发明授权
    Memory subsystem calibration using substitute results 有权

    公开(公告)号：US11776597B2

    公开(公告)日：2023-10-03

    申请号：US17646741

    申请日：2022-01-03

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

    IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/1076 ,  G11C7/10 ,  G11C2207/2254

    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

    Duty cycle correction with read and write calibration
    39.
    发明授权
    Duty cycle correction with read and write calibration 有权

    公开(公告)号：US10734983B1

    公开(公告)日：2020-08-04

    申请号：US16277263

    申请日：2019-02-15

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Yanzhe Liu

    IPC: G11C11/409 ,  H03K3/017 ,  H03K5/156

    Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

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