公开(公告)号：US20070009061A1

公开(公告)日：2007-01-11

申请号：US11522154

申请日：2006-09-15

申请人： Takashi Kaku ,  Kyoko Hirao

发明人： Takashi Kaku ,  Kyoko Hirao

IPC分类号： H04L27/00 ,  H04K1/10

CPC分类号： H04L27/2628 ,  H04L1/0071 ,  H04L27/2602 ,  H04L27/2614 ,  H04L27/265

摘要： A data transmission method comprises the steps of: a) performing two-dimensional interleaving along a time axis and along a frequency axis; b) transmitting the thus-obtained data by a multi-carrier transmission form; and c) producing, by channel copy operation, data which is short for the number of channels required for fast inverse Fourier transform performed antecedent and subsequent to said step a).

摘要翻译： 数据传输方法包括以下步骤：a）沿时间轴和频率轴执行二维交织; b）通过多载波传输形式发送由此获得的数据; 以及c）通过信道复制操作产生对于先前执行的快速傅里叶逆变换所需的信道数量以及所述步骤a）之后的数据。

公开(公告)号：US06898256B2

公开(公告)日：2005-05-24

申请号：US10319927

申请日：2002-12-12

申请人： Takashi Kaku ,  Takahiro Kurakata ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Takahiro Kurakata ,  Hideo Miyazawa

IPC分类号： H04L7/02 ,  H04L7/06 ,  H04L27/26 ,  H04L27/34 ,  H04L7/00

CPC分类号： H04L27/2613 ,  H04J7/00 ,  H04L7/06 ,  H04L27/2656 ,  H04L27/3455

摘要： In a synchronization method and apparatus in a data transmission using a transparent transmission line, a periodic amplitude modulation is applied, or a zero-point is inserted, as a synchronizing signal to a transmission signal point on a transmission side at a preceding stage of a transparent transmission line. Also, in case of a frame synchronization, a power value of a received signal is calculated on a reception side of the above-mentioned transparent transmission line and the synchronizing signal is vectorized using the power values whose phases are different from each other by 90 degrees on a time axis.

摘要翻译： 在使用透明传输线的数据传输的同步方法和装置中，施加周期性幅度调制或插入零点作为同步信号到发送侧的发送信号点，在前一阶段 透明传输线。 此外，在帧同步的情况下，在上述透明传输线的接收侧计算接收信号的功率值，并且使用相位彼此不同的功率值向量化同步信号90度 在时间轴上。

公开(公告)号：US06882684B2

公开(公告)日：2005-04-19

申请号：US09756793

申请日：2001-01-10

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04L27/38 ,  H03G3/30 ,  H04L27/08 ,  H04L27/34 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L27/34 ,  H03G3/3089 ,  H04L27/08

摘要： An automatic gain control circuit includes a first portion which calculates a first error amount, and a second portion which calculates a second error amount. Both calculated error amount is sent to a determination module. Further, an integrator integrates an error amount, a difference between a power of an input signal and an average power of an eye pattern for example. The determination determines whether the integrated error amount exceeds a predetermined value or not, and output either of the first error amount and the second error amount based on the determination.

摘要翻译： 自动增益控制电路包括计算第一误差量的第一部分和计算第二误差量的第二部分。 两个计算出的错误量被发送到确定模块。 此外，积分器将误差量，输入信号的功率与眼图的平均功率之间的差异进行积分。 该判定是否确定积分误差量是否超过预定值，并且基于该确定来输出第一误差量和第二误差量中的任一个。

公开(公告)号：US06377647B1

公开(公告)日：2002-04-23

申请号：US09205804

申请日：1998-12-04

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H03D324

CPC分类号： H03L7/091 ,  H04L7/0331

摘要： A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.

摘要翻译： PLL电路使内部振荡信号锁定到外部输入时钟信号，并且能够抑制抖动。 PLL电路包括用于对输入时钟信号进行分频的分频电路; 压控振荡器; 一个缺失脉冲时钟信号产生电路，用于根据压控振荡器的输出信号创建一个具有比分频电路的输出信号高的缺失脉冲时钟信号， 脉冲部分 相位比较器电路，用于通过使用缺失脉冲时钟信号对分频电路的输出信号进行采样; 移位寄存器，用于存储相位比较器电路的输出信号的变化; 以及数字信号处理电路，用于将存储在移位寄存器中的值转换为相位差，并且用于基于相位差控制到压控振荡器的输入电压。

公开(公告)号：US6104758A

公开(公告)日：2000-08-15

申请号：US925181

申请日：1997-09-09

申请人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

IPC分类号： H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H04B3/04 ,  H04L25/03 ,  H04L27/34 ,  H04L5/12

CPC分类号： H04L27/3411 ,  H04L25/03343 ,  H04L25/4975 ,  H04L27/34

摘要： A transfer process in which, an original vector signal is precoded to an intermediately-precoded vector signal, and the extended modulo operation is performed when the intermediately-precoded vector signal is located outside a predetermined extended-modulo limit area, and the precoded vector signal is transferred through a system having a predetermined filtering characteristic. From the transferred vector signal, the original vector signal is detected, based on a relationship between the vector components of the original vector signal and the transferred vector signal.

公开(公告)号：US5963593A

公开(公告)日：1999-10-05

申请号：US825067

申请日：1997-03-27

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

IPC分类号： H03H17/00 ,  H04B3/04 ,  H04B3/10 ,  H03H7/40 ,  H03H5/00

CPC分类号： H04B3/04 ,  H04L25/03885

摘要： A method of controlling a line equalizer such as a modem includes an extracting step of extracting plural tone signals each superimposed on a transmission signal and having a specific frequency component; a judging step of judging levels of the extracted tone signals; and a controlling step of controlling characteristic of a line equalizer which equalizes a receive signal, based on the levels of the judged tone signals. A line equalizer is controlled without performing an exchange of a training signal prior to starting a data transmission and without increasing the amount of hardware of a modem or the like.

摘要翻译： 一种控制诸如调制解调器之类的线路均衡器的方法包括一个提取步骤，提取叠加在传输信号上并具有特定频率分量的多个音调信号; 判断步骤，用于判断所提取的音调信号的电平; 以及控制步骤，基于所判断的音调信号的电平来控制均衡接收信号的线均衡器的特性。 在开始数据传输之前不必执行训练信号的交换，而不增加调制解调器等的硬件量，可以控制线路均衡器。

公开(公告)号：US5757865A

公开(公告)日：1998-05-26

申请号：US553990

申请日：1995-11-06

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H04L27/38 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233 ,  H04L27/06

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0055

摘要： The invention provides a carrier phase control circuit which can eliminate a phase intercept fluctuation so that, when the carrier phase control circuit is applied to a very high speed modem having a communication speed of, for example, 28.8 kbps, occurrence of a communication error can be suppressed and the modem has an improved characteristic. The carrier phase control circuit is provided on a reception side of a communication apparatus and interposed between an automatic equalizer and a signal decision section. The carrier phase control circuit includes a frequency offset removal section for predicting and removing an offset of a frequency of a transmission signal based on an output of the automatic equalizer, and a phase intercept variation removal section for predicting and removing a phase intercept variation of the transmission signal based on an output of the frequency offset removal section and inputting a resulted signal as an output thereof to the signal decision section.

摘要翻译： 本发明提供了一种载波相位控制电路，其可以消除相位截距波动，使得当载波相位控制电路被应用于具有例如28.8kbps的通信速度的非常高速的调制解调器时，可能发生通信错误 被抑制，调制解调器具有改进的特性。 载波相位控制电路设置在通信装置的接收侧，并插入在自动均衡器和信号判定部分之间。 载波相位控制电路包括：频率偏移消除部分，用于基于自动均衡器的输出来预测和去除发送信号频率的偏移;相位截距变化去除部分，用于预测和去除发送信号的相位截距变化， 基于频率偏移去除部的输出的发送信号，并将得到的信号作为其输出输入到信号判定部。

公开(公告)号：US5631923A

公开(公告)日：1997-05-20

申请号：US89190

申请日：1993-07-12

申请人： Takashi Kaku ,  Toyomi Obikawa

发明人： Takashi Kaku ,  Toyomi Obikawa

IPC分类号： H04B3/23 ,  H04L1/22 ,  H04L5/14 ,  H04L25/02 ,  H04L25/06 ,  H04L27/00 ,  H04L29/14 ,  H03D3/24

CPC分类号： H04L25/0262 ,  H04B3/23 ,  H04L1/22 ,  H04L25/068 ,  H04L5/143

摘要： In a modem, after scrambling data which are time-divided into main data and secondary data, a 2 W-4 W conversion circuit sends the data to the two-wire line. An estimated echo component is subtracted from a signal which is available from the 2 W-4 W conversion circuit. Following this, the signal from the 2 W-4 W conversion circuit is demodulated, descrambled and separated into main data and secondary data. A generator polynomial for scrambling is different from a generator polynomial for descrambling. The modem comprises a line-trouble-detect part which samples data of the secondary channel, by multipoint sampling, to obtain the secondary data and detects the number of inversion points in the descrambled secondary channel data per unit time period. The line-trouble-detect part outputs a line-trouble signal which indicates that there is a trouble on the line if the number of detected inversion points is more than a predetermined number.

摘要翻译： 在调制解调器中，在将分组成主数据和次数据的数据进行加扰之后，2W-4W转换电路将数据发送到双线线路。 从可从2 W-4 W转换电路获得的信号中减去估计的回波分量。 此后，来自2W-4W转换电路的信号被解调，解扰并分离成主数据和次数据。 用于扰码的生成多项式与用于解扰的生成多项式不同。 调制解调器包括线路故障检测部分，其通过多点采样来对二次信道的数据进行采样，以获得二次数据，并且检测每单位时间段内解扰的次级信道数据中的反转点的数量。 线路故障检测部分输出线路故障信号，如果检测到的反转点的数量大于预定数量，则该线路故障信号指示线路上存在故障。

公开(公告)号：US5583887A

公开(公告)日：1996-12-10

申请号：US31621

申请日：1993-03-15

申请人： Hiroyasu Murata ,  Takashi Kaku

发明人： Hiroyasu Murata ,  Takashi Kaku

IPC分类号： H04L27/00 ,  H03H17/00 ,  H03H17/06 ,  H04J1/05 ,  H04L25/05 ,  H03H7/30 ,  H04L27/04

CPC分类号： H03H17/0657 ,  H04J1/05 ,  H04L25/05

摘要： A roll off filter portion for an input transmission point signal executes a roll-off filtering process and an interpolation process with a multiple of two at the same time. The roll-off filtering process is adapted to form a frequency spectrum characteristic in a cosine roll-off shape for the input signal. An interpolator portion, connected to the roll-off filter portion, executes an interpolation process with a multiple of two. This process is a filtering process for forming a frequency spectrum characteristic in a cosine roll-off shape for an input signal. Depending on what multiple of the original sampling frequency a transmission point signal is interpolated, a corresponding number of the interpolator portions are connected in a cascade shape. when a plurality of channels of transmission point signals are modulated and multiplexed according to an FDM system, a corresponding number of signal processing systems are disposed according to the plurality of transmission point signals with different modulation rates.

摘要翻译： 用于输入传输点信号的滚降滤波器部分同时执行滚降滤波处理和两个倍数的内插处理。 滚降滤波处理适用于形成用于输入信号的余弦滚降形状的频谱特性。 连接到滚降滤波器部分的内插器部分以两倍的倍数执行内插处理。 该处理是用于形成用于输入信号的余弦滚降形状的频谱特性的滤波处理。 根据传输点信号的原始采样频率的多少来内插，相应数量的内插器部分以级联形式连接。 当根据FDM系统对多个传输点信号进行调制和复用时，根据具有不同调制速率的多个传输点信号设置相应数量的信号处理系统。

公开(公告)号：US5574737A

公开(公告)日：1996-11-12

申请号：US53803

申请日：1993-04-29

申请人： Yasunao Mizutani ,  Takashi Kaku

发明人： Yasunao Mizutani ,  Takashi Kaku

IPC分类号： H04L7/04 ,  H04L27/38 ,  H04L1/00 ,  H04L7/10

CPC分类号： H04L27/38 ,  H04L7/048

摘要： A modulator-demodulator device includes a transmitter side having an error control coding circuit for adding redundancy to a bit sequence to be transmitted from a bit processing circuit and coding the bit sequence. A data sequence to coordinate transforming circuit transforms the bit sequence from the error control circuit into a signal point coordinate on a complex plane. A coordinate rotating circuit rotates the transformed signal point coordinates based on frame phase information from a frame phase generating circuit. In the receiver side, a coordinate rotating circuit applies rotation in a direction reverse that of the transmitter coordinate rotating circuit based on the frame phase information from the frame phase generating circuit. A second decision circuit decides the maximum likelihood signal point by utilizing the redundancy added by the error control coding circuit of the transmitter side and correcting the coordinate error of the received signal point. An unsynchronized frame state deciding circuit decides the unsynchronized frame state based on the distance between the decision point determined by the maximum likelihood signal point deciding circuit and the demodulated received signal point on the complex plane, so that the synchronized frame state is quickly detected. An evaluation value is designated for each of the transition sequence of signals, and in the receiver side, error control signal decoding is carried out so that the transition sequence of the maximum likelihood received signal is selected based on the updated evaluation value and the error in the demodulated signal is corrected, so that the error in the data transmission is corrected.

摘要翻译： 调制器 - 解调器装置包括发射机侧，发射机侧具有用于将比特序列从比特处理电路发送的比特序列加上冗余的错误控制编码电路，并对该比特序列进行编码。 坐标变换电路的数据序列将位序列从误差控制电路变换为复平面上的信号点坐标。 坐标旋转电路基于来自帧相位产生电路的帧相位信息来旋转经变换的信号点坐标。 在接收侧，基于来自帧相位产生电路的帧相位信息，坐标旋转电路沿与发送器坐标旋转电路相反的方向施加旋转。 第二判定电路利用由发送器侧的误差控制编码电路所附加的冗余来校正接收信号点的坐标误差来决定最大似然信号点。 不同步的帧状态决定电路基于由最大似然信号点判定电路决定的判定点与复平面上的解调接收信号点之间的距离来决定不同步的帧状态，从而快速检测同步的帧状态。 针对每个信号的转换序列指定评估值，在接收机侧，执行错误控制信号解码，使得根据更新后的评估值和误差来选择最大似然接收信号的转换序列 解调信号被校正，从而校正数据传输中的误差。