A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.