发明授权
US5574737A Modulator-demodulator device capable of detecting an unsynchronized frame state based on hard and soft error values 失效
调制解调器能够基于硬和软错误值检测不同步的帧状态

  • 专利标题: Modulator-demodulator device capable of detecting an unsynchronized frame state based on hard and soft error values
  • 专利标题(中): 调制解调器能够基于硬和软错误值检测不同步的帧状态
  • 申请号: US53803
    申请日: 1993-04-29
  • 公开(公告)号: US5574737A
    公开(公告)日: 1996-11-12
  • 发明人: Yasunao MizutaniTakashi Kaku
  • 申请人: Yasunao MizutaniTakashi Kaku
  • 申请人地址: JPX Kawasaki
  • 专利权人: Fujitsu Limited
  • 当前专利权人: Fujitsu Limited
  • 当前专利权人地址: JPX Kawasaki
  • 优先权: JPX1-151272 19890613; JPX1-164624 19890627
  • 主分类号: H04L7/04
  • IPC分类号: H04L7/04 H04L27/38 H04L1/00 H04L7/10
Modulator-demodulator device capable of detecting an unsynchronized
frame state based on hard and soft error values
摘要:
A modulator-demodulator device includes a transmitter side having an error control coding circuit for adding redundancy to a bit sequence to be transmitted from a bit processing circuit and coding the bit sequence. A data sequence to coordinate transforming circuit transforms the bit sequence from the error control circuit into a signal point coordinate on a complex plane. A coordinate rotating circuit rotates the transformed signal point coordinates based on frame phase information from a frame phase generating circuit. In the receiver side, a coordinate rotating circuit applies rotation in a direction reverse that of the transmitter coordinate rotating circuit based on the frame phase information from the frame phase generating circuit. A second decision circuit decides the maximum likelihood signal point by utilizing the redundancy added by the error control coding circuit of the transmitter side and correcting the coordinate error of the received signal point. An unsynchronized frame state deciding circuit decides the unsynchronized frame state based on the distance between the decision point determined by the maximum likelihood signal point deciding circuit and the demodulated received signal point on the complex plane, so that the synchronized frame state is quickly detected. An evaluation value is designated for each of the transition sequence of signals, and in the receiver side, error control signal decoding is carried out so that the transition sequence of the maximum likelihood received signal is selected based on the updated evaluation value and the error in the demodulated signal is corrected, so that the error in the data transmission is corrected.
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