公开(公告)号：US20050081017A1

公开(公告)日：2005-04-14

申请号：US10685654

申请日：2003-10-14

Applicant: Jeffrey Rupley ,  Edward Brekelbaum ,  Edward Grochowski ,  Bryan Black

Inventor： Jeffrey Rupley ,  Edward Brekelbaum ,  Edward Grochowski ,  Bryan Black

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

Abstract translation: 公开了一种用于使用微操作来实现预定指令的装置，系统和方法。 微码引擎接收指令，分解指令，并产生多个微操作来实现该指令。 每个分解的微操作指示单个目的地寄存器。 对于预测指令，分解的微操作包括在两个潜在输出值之间选择的“条件移动”微操作。 除了在一个潜在输出值是常数的情况下，用于预测指令的分解的微操作还包括将目的地寄存器的输入值保存在临时变量中的附加指令。 对于至少一个实施例，用于预测指令的限定谓词附加到存储在临时寄存器中的输入值。

公开(公告)号：US06839814B2

公开(公告)日：2005-01-04

申请号：US10726492

申请日：2003-12-04

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US06675266B2

公开(公告)日：2004-01-06

申请号：US09750094

申请日：2000-12-29

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F1200

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并且被设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的实施例，标签阵列存储电路包括耦合在一起以形成n位存储单元的多个存储器位电路和耦合到n位存储单元的有效位电路，有效位 电路被配置为与多个存储器位电路同时访问。

公开(公告)号：US6035389A

公开(公告)日：2000-03-07

申请号：US132043

申请日：1998-08-11

Applicant: Edward Grochowski ,  Hans Mulder ,  Derrick C. Lin

Inventor： Edward Grochowski ,  Hans Mulder ,  Derrick C. Lin

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3863

Abstract: An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers.

Abstract translation: 一种装置包括产生脉冲的时钟和具有多个行和一个或多个端口的电子硬件结构。 每行适于记录通过其中一个端口写入的单独的延迟矢量。 其中记录的等待时间向量响应时钟。 在处理器中调度指令的方法包括将多个预期延迟更新为寄存器延迟表的行的一部分，并且响应于时钟脉冲减少其余行中剩余的预期延迟。 该部分的行对应于特定寄存器。

公开(公告)号：US5586276A

公开(公告)日：1996-12-17

申请号：US301313

申请日：1994-09-06

Applicant: Edward Grochowski ,  Kenneth Shoemaker

Inventor： Edward Grochowski ,  Kenneth Shoemaker

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/30152 ,  G06F9/3816 ,  G06F9/3885

Abstract: Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.

Abstract translation: 用于当指令长度变化并且顺序地出现在指令流中时确定由计算机系统处理的指令的长度的装置，而不区分指令，包括用于为指令的每个预定指定长度提供结束位的装置，以指示指令结束 在其长度的那一点上，用于将作为指令的实际结束的指令的特定预定长度的结束位设置用于依次处理第一指令的第一通道，用于处理下一个指令的第二通道 第一指令和用于查看由第一通道正在处理的指令的结束位的装置，以从指令流确定该指令的终点和下一个指令的开始。

公开(公告)号：US20170199825A1

公开(公告)日：2017-07-13

申请号：US15384054

申请日：2016-12-19

Applicant: Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0864 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US20130219399A1

公开(公告)日：2013-08-22

申请号：US13843164

申请日：2013-03-15

Applicant: Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

Inventor： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

IPC: G06F9/48

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20110154000A1

公开(公告)日：2011-06-23

申请号：US12653800

申请日：2009-12-18

Applicant: Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

Inventor： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3004 ,  G06F9/30087

Abstract: A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.

Abstract translation: 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

公开(公告)号：US07395304B2

公开(公告)日：2008-07-01

申请号：US10890848

申请日：2004-07-13

Applicant: Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

Inventor： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC: G06F7/04

CPC classification number: G06F7/5095 ,  G06F7/02 ,  G06F7/4824

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.

Abstract translation: 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。 可以在整个电路中不传播进位信号来实现上述所有操作。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。 如果算术运算是减法，则该调整使得运算电路作为减法运算的结果以冗余形式产生有效结果。 然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

公开(公告)号：US06954848B2

公开(公告)日：2005-10-11

申请号：US10038038

申请日：2002-01-02

Applicant: Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

Inventor： Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Abstract translation: 在第一次指令将数据加载到寄存器中之后，监视寄存器以查看是否在下一个时钟周期读取。 当数据在下一个时钟周期内未被读取时，指令被分类为慢指令。 与指令相关联的指令地址用于更新历史表。 历史表存储用于指示指令是指令是慢指令还是非慢指令的信息。 当第二次遇到指令的指令地址时，使用历史表来确定指令是可慢还是不慢。