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    Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby
    31.
    发明授权
    Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby 有权
    选择性地去除相变存储单元的导电底电极的一侧的方法及由此得到的结构

    公开(公告)号：US07229887B2

    公开(公告)日：2007-06-12

    申请号：US10340506

    申请日：2003-01-10

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L21/20

    CPC classification number: H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode.The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

    Abstract translation: 本发明涉及一种相变存储器件。 该装置包括设置在第一电介质的凹部中的下电极。 下电极包括第一侧和第二侧。 第一面与一定量的相变记忆材料通信。 第二面的长度小于第一面。 此外，第二电介质可以覆盖在下电极上。 第二电介质具有与下电极基本相似的形状。 本发明还涉及一种制造相变存储器件的方法。 该方法包括在凹部中提供下电极材料。 该方法还包括移除第二侧的至少一部分。

    Increasing phase change memory column landing margin
    33.
    发明申请
    Increasing phase change memory column landing margin 有权
    增加相变记忆柱着陆边界

    公开(公告)号：US20070096073A1

    公开(公告)日：2007-05-03

    申请号：US11262250

    申请日：2005-10-28

    Applicant: Charles Dennison ,  Ilya Karpov

    Inventor： Charles Dennison ,  Ilya Karpov

    IPC: H01L29/04

    CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1675

    Abstract: A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.

    Abstract translation: 可以形成具有较高列着陆边缘的相变存储器。 在一种方法中，可以通过增加电极的高度来增加列着色边缘。 例如，电极由两种不同的材料制成，其中之一包括氮化物，另一个不包括氮化物。 在另一种方法中，使用与覆盖和围绕的绝缘体基本上相同的材料的硬掩模。 硬掩模和下面的相变材料由与硬掩模不同的材料的侧壁间隔物保护。 如果硬掩模和绝缘体具有基本相同的蚀刻特性，则可以去除硬掩模，同时保持侧壁间隔物的保护特性。

    Reducing oxidation of phase change memory electrodes
    34.
    发明申请
    Reducing oxidation of phase change memory electrodes 审中-公开

    公开(公告)号：US20060289848A1

    公开(公告)日：2006-12-28

    申请号：US11168780

    申请日：2005-06-28

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L29/04

    CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1675

    Abstract: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.

    Shared address lines for crosspoint memory
    36.
    发明申请
    Shared address lines for crosspoint memory 有权
    用于交叉点内存的共享地址行

    公开(公告)号：US20060120136A1

    公开(公告)日：2006-06-08

    申请号：US11202428

    申请日：2005-08-11

    Applicant: Charles Dennison ,  Tyler Lowrey

    Inventor： Charles Dennison ,  Tyler Lowrey

    IPC: G11C11/00

    CPC classification number: G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

    Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

    Abstract translation: 交叉点存储器包括共享地址线。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的单元。 可以使用电压偏置来选择一个单元，并且取消选择另一个单元。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造并降低成本。

    Lower electrode isolation in a double-wide trench and method of making same
    37.
    发明授权
    Lower electrode isolation in a double-wide trench and method of making same 失效
    双沟槽中的较低电极隔离及其制造方法

    公开(公告)号：US06969633B2

    公开(公告)日：2005-11-29

    申请号：US10652631

    申请日：2003-08-29

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: G11C8/02 ,  H01L27/24 ,  H01L21/00

    CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: The invention relates to a phase-change memory device. The device includes a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode. Additionally, other isolated lower electrodes may be formed along a symmetry line that is orthogonal to the first two isolated lower electrodes. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation structure s around a memory cell structure diode stack.

    Abstract translation: 本发明涉及一种相变存储器件。 该器件包括双宽沟槽，其中沉积单个膜，但是由其形成两个隔离的下电极。 此外，形成与下电极连通的二极管叠层。 此外，可以沿着与前两个隔离的下电极正交的对称线形成其它隔离的下电极。 本发明还涉及一种制造相变存储器件的方法。 该方法包括在存储单元结构二极管堆叠周围形成两个正交和相交的隔离结构。

    Semiconductor assemblies
    38.
    发明申请
    Semiconductor assemblies 失效
    半导体组件

    公开(公告)号：US20050194659A1

    公开(公告)日：2005-09-08

    申请号：US11116472

    申请日：2005-04-27

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: H01L21/763 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L29/00

    CPC classification number: H01L21/76831 ,  H01L21/763 ,  H01L21/76802 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material. The invention also includes a semiconductor assembly comprising an anti-fuse construction and an electrically conductive interconnect construction.

    Abstract translation: 本发明包括半导体处理方法，其中跨越第一电节点和第二电节点形成绝缘体。 质量体具有延伸穿过其中的电气节点的一对开口。 各个开口各自具有由电节点中的一个和至少一个侧壁限定的外围。 一个开口延伸到第一电节点并且是第一开口，另一个开口延伸到第二电节点并且是第二开口。 在开口内形成介电材料层以使开口变窄。 在狭窄的开口内形成导电材料塞。 第一开口内的导电材料塞是第一材料塞，并且通过电介质材料与第一电​​节点分离; 并且所述第二开口内的导电插塞是第二材料塞，并且不通过所述电介质材料与所述第二电节点分离。 本发明还包括一种包括反熔丝结构和导电互连结构的半导体组件。

    Use of gate electrode workfunction to improve DRAM refresh
    39.
    发明申请
    Use of gate electrode workfunction to improve DRAM refresh 有权
    使用栅电极功能来改善DRAM刷新

    公开(公告)号：US20050173746A1

    公开(公告)日：2005-08-11

    申请号：US11105412

    申请日：2005-04-14

    Applicant: Charles Dennison

    Inventor： Charles Dennison

    IPC: G11C11/406 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10873 ,  G11C11/406 ,  H01L27/10811

    Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

    Abstract translation: 本发明涉及一种方法和结果，其中可以通过使用用于晶体管栅电极的硅中间隙材料来制造DRAM，从而改善存取晶体管的刷新特性。 可以以降低的衬底掺杂要求来设定阈值电压。 此过程也能改善电流泄漏。

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