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    Method of Gap Filling For Semiconductor Device
    301.
    发明申请
    Method of Gap Filling For Semiconductor Device 有权

    公开(公告)号：US20210226038A1

    公开(公告)日：2021-07-22

    申请号：US17226755

    申请日：2021-04-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Te-Yang Lai ,  Che-Hao Chang ,  Chi On Chui

    IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

    Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flow able oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

    Negative-Capacitance Field Effect Transistor
    309.
    发明申请
    Negative-Capacitance Field Effect Transistor 审中-公开

    公开(公告)号：US20200176585A1

    公开(公告)日：2020-06-04

    申请号：US16596059

    申请日：2019-10-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51

    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

    Low-K gate spacer and formation thereof
    310.
    发明授权
    Low-K gate spacer and formation thereof 有权

    公开(公告)号：US10510612B2

    公开(公告)日：2019-12-17

    申请号：US16203814

    申请日：2018-11-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

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