公开(公告)号：US20240339443A1

公开(公告)日：2024-10-10

申请号：US18401694

申请日：2024-01-01

申请人： POWERTECH TECHNOLOGY INC.

发明人： Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC分类号： H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/167 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/83

摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.

公开(公告)号：US20240339378A1

公开(公告)日：2024-10-10

申请号：US18473665

申请日：2023-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： Jong Ryeol YOO

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/76804 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/092

摘要： A semiconductor device includes a substrate including a substrate having a first side and a second side, a source/drain pattern on a fin-shaped pattern and connected to the fin-shaped pattern, a source/drain contact on the source/drain pattern and connected to the source/drain pattern, and a buried conductive pattern includes a first portion and a second portion, the second portion of between the first portion of the buried conductive pattern and a contact connecting via, at the first portion of the buried conductive pattern a width of the buried conductive pattern in a third direction decreases as the buried conductive pattern goes away from a back wiring line, and at the second portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction increases, as the buried conductive pattern goes away from the back wiring line.

公开(公告)号：US12113132B2

公开(公告)日：2024-10-08

申请号：US18053021

申请日：2022-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20240332239A1

公开(公告)日：2024-10-03

申请号：US18191950

申请日：2023-03-29

申请人： International Business Machines Corporation

发明人： Nicholas Alexander Polomoff ,  Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Eric Perfecto ,  Katsuyuki Sakuma ,  SPYRIDON SKORDAS

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/20 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/95

摘要： A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.

公开(公告)号：US20240332186A1

公开(公告)日：2024-10-03

申请号：US18609065

申请日：2024-03-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinbum KIM

IPC分类号： H01L23/528 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a substrate having opposite first and second surfaces, a fin-type active pattern on the first surface of the substrate, a gate structure intersecting the fin-type active pattern, a source/drain region on the fin-type active pattern at a side of the gate structure, a contact structure connected to the source/drain region, a buried conductive structure electrically connected to the contact structure and extending in a direction perpendicular to the first surface, and a conductive through structure extending from the second surface of the substrate toward the first surface of the substrate and contacting with the buried conductive structure, the conductive through structure has a first width at a level adjacent to the first surface, narrower than a second width at a level adjacent to the second surface.

公开(公告)号：US20240332150A1

公开(公告)日：2024-10-03

申请号：US18401872

申请日：2024-01-02

申请人： Samsung Electronics Co., Ltd.

发明人： Hwanjoo PARK ,  Sunggu KANG ,  Jaechoon KIM

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431

摘要： A semiconductor package includes a first redistribution wiring layer having first redistribution wirings; a first lower semiconductor chip and a second lower semiconductor chip spaced apart from each other on the first redistribution wiring layer; a sealing member covering the first lower semiconductor chip and the second lower semiconductor chip on the first redistribution wiring layer; a plurality of conductive vias penetrating the sealing member between the first lower semiconductor chip and the second lower semiconductor chip; a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of conductive vias; an upper semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings; and a first heat dissipation block and a second heat dissipation block respectively disposed on the first lower semiconductor chip and the second lower semiconductor chip.

公开(公告)号：US20240332130A1

公开(公告)日：2024-10-03

申请号：US18192989

申请日：2023-03-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joshua M. Rubin ,  Marc A. Bergendahl

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L21/6835 ,  H01L2221/68359

摘要： Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a first horizontally-fabricated semiconductor die section and a vertical interconnect (VI) die perpendicularly oriented to the first semiconductor die section. The VI die may include vertical metal interconnect lines electrically connecting components above and below the VI die.

公开(公告)号：US12107109B2

公开(公告)日：2024-10-01

申请号：US18191218

申请日：2023-03-28

申请人： Samsung Electronics Co., Ltd.

发明人： Yi Koan Hong ,  Taeseong Kim

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L27/146

CPC分类号： H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2224/08146 ,  H01L2224/80894

摘要： A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US12107078B2

公开(公告)日：2024-10-01

申请号：US18229627

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang ,  Chia-Ping Lai

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/525 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5256 ,  H01L2225/06541

摘要： A semiconductor die includes a first semiconductor substrate; a first interconnect structure disposed on a front side of the first semiconductor substrate; a first through-substrate via (TSV) structure extending through the first semiconductor substrate; and a first fuse structure disposed between and electrically connecting the TSV structure and the first interconnect structure.

公开(公告)号：US12106970B2

公开(公告)日：2024-10-01

申请号：US17919520

申请日：2021-04-02

申请人： BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.

发明人： Qiushi Xie ,  Xiaoping Shi ,  Qingjun Zhou ,  Dongsan Li ,  Chun Wang ,  Yiming Zhang

IPC分类号： H01L21/308 ,  H01L23/48

CPC分类号： H01L21/3081 ,  H01L23/481

摘要： The present disclosure discloses a pattern sheet, a semiconductor intermediate product, and a hole etching method. The pattern sheet includes a substrate, a dielectric layer, and a mask structure. The mask structure includes a multi-layer mask layer. An uppermost mask layer is a photoresist layer. A thickness of each layer of the mask layer and etching selectivity ratios between the layers below the mask layer satisfy that in each two neighboring layers of the mask layer, a lower layer of the mask layer is etched to form a through-hole penetrating a thickness of the lower layer of the mask layer, a remaining thickness of the upper layer of the mask layer is greater than or equal to zero.