公开(公告)号：US12193343B2

公开(公告)日：2025-01-07

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H10N70/00 ,  H01L29/423 ,  H10B63/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.

公开(公告)号：US20250008847A1

公开(公告)日：2025-01-02

申请号：US18884913

申请日：2024-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Massimo Borghi

IPC: H10N70/20 ,  G11C13/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.

公开(公告)号：US20250008745A1

公开(公告)日：2025-01-02

申请号：US18221872

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20 ,  H10N79/00

Abstract: An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

公开(公告)号：US12185554B2

公开(公告)日：2024-12-31

申请号：US17574422

申请日：2022-01-12

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita ,  Chi Shun Lin

IPC: H10B63/00 ,  G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H10N70/00

Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local source line, bit lines, and a shared source line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local source line extends in a column direction of the array area. The bit lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared source line is connected to the local source line. The shared source line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

公开(公告)号：US12185553B2

公开(公告)日：2024-12-31

申请号：US17715065

申请日：2022-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Chih-Chao Huang ,  Ming-Che Lin ,  Frederick Chen ,  Han-Huei Hsu

IPC: H10B63/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H10N70/00

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

公开(公告)号：US12178054B2

公开(公告)日：2024-12-24

申请号：US17677577

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H10B63/00 ,  G11C13/00 ,  H10B20/00 ,  H10N70/00

Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.

公开(公告)号：US12175358B2

公开(公告)日：2024-12-24

申请号：US17248373

申请日：2021-01-22

Applicant: Commissariat à I'Energie Atomique et aux Energies Alternatives ,  Universität Zürich

Inventor： Thomas Dalgaty ,  Giacomo Indiveri ,  Melika Payvand ,  Elisas Vianello

IPC: G06N3/063 ,  G06N3/04 ,  H10B63/00

Abstract: The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell (302) having an input coupled to a first input line (304) of the routing circuit and an output coupled to a first column line (308); a second memory cell (302) having an input coupled to a second input line (304) of the routing circuit and an output coupled to the first column line (308); and a first comparator circuit (310) configured to compare a signal (IREAD1) on the first column line (308) with a reference level, and to selectively assert a signal (VOUT1) on a first output line (312) of the routing circuit based on the comparison.

公开(公告)号：US20240423105A1

公开(公告)日：2024-12-19

申请号：US18335026

申请日：2023-06-14

Applicant: TetraMem Inc.

Inventor： Minxian Zhang ,  Ning Ge

IPC: H10N70/00 ,  H10B63/00

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, an interface layer fabricated on the first electrode, a switching oxide layer comprising at least one transition metal oxide; and a second electrode fabricated on the switching oxide layer. The interface layer may include a discontinuous layer of a dielectric material and a conductive material deposited in the discontinuous layer of the dielectric material. The interface layer is positioned between the first electrode and the switching oxide layer. The dielectric material may be and/or include Al2O3, SiO2, Si3N4, MgO, Y2O3, Gb2O3, Sm2O3, CeO2, Er2O3, La2O3, etc. The conductive material may include a metal, a conductive oxide, a conductive nitride, etc.

公开(公告)号：US20240413247A1

公开(公告)日：2024-12-12

申请号：US18329606

申请日：2023-06-06

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Chang Chiang ,  Katherine H. Chiang ,  Yen-Chung Ho ,  Ming-Yen Chuang ,  Chung-Te Lin

IPC: H01L29/786 ,  H01L21/4757 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

Abstract: A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.

公开(公告)号：US12167703B2

公开(公告)日：2024-12-10

申请号：US18321347

申请日：2023-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.