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公开(公告)号：US20250048944A1
公开(公告)日：2025-02-06
申请号：US18237915
申请日：2023-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kai-Jiun Chang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, and a resistive switching structure embedded in an upper portion of the conductive via. The resistive switching structure includes a top electrode layer having a lower sharp corner, a resistive switching material layer disposed around the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistive switching material layer and the upper portion of the conductive via.
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公开(公告)号：US20250008745A1
公开(公告)日：2025-01-02
申请号：US18221872
申请日：2023-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kai-Jiun Chang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.
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公开(公告)号：US20240188306A1
公开(公告)日：2024-06-06
申请号：US18096532
申请日：2023-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang , Hsiang-Hung Peng
IPC: H10B63/00
CPC classification number: H10B63/82
Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.
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公开(公告)号：US20240431219A1
公开(公告)日：2024-12-26
申请号：US18224054
申请日：2023-07-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: An RRAM includes a bottom electrode, a resistive switching layer, a top electrode and a cap layer stacked from bottom to top. The cap layer includes a top surface. A first spacer contacts a first sidewall of the bottom electrode, and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and contacts a third spacer of the top electrode. A thickness of the first spacer is greater of a thickness of the second spacer. The first spacer and the second spacer do not cover the topmost surface of the cap layer.
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公开(公告)号：US20240260490A1
公开(公告)日：2024-08-01
申请号：US18112483
申请日：2023-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
CPC classification number: H10N70/8418 , H10N70/011 , H10N70/24 , H10N70/8833
Abstract: A resistive memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; and a memory stack structure disposed on the conductive via and the dielectric layer. The memory stack structure includes a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer. The top electrode layer includes at least two physically separated sub-electrode portions.
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Patent Agency Ranking
公开(公告)号：US20250017121A1
公开(公告)日：2025-01-09
申请号：US18449716
申请日：2023-08-15
Applicant: United Microelectronics Corp.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.
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公开(公告)号：US20250008849A1
公开(公告)日：2025-01-02
申请号：US18221385
申请日：2023-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Min Ting , Chuan-Fu Wang , Yu-Huan Yeh
Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode, a spacer covering a sidewall of the resistive switching layer and a sidewall of the bottom electrode, and a top electrode capping the spacer and the resistive switching layer.
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公开(公告)号：US20240407274A1
公开(公告)日：2024-12-05
申请号：US18219717
申请日：2023-07-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.
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公开(公告)号：US20240407273A1
公开(公告)日：2024-12-05
申请号：US18218602
申请日：2023-07-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Hsiang-Hung Peng , Yu-Huan Yeh , Chuan-Fu Wang
Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.
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公开(公告)号：US20240107902A1
公开(公告)日：2024-03-28
申请号：US17970560
申请日：2022-10-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Yu-Huan Yeh , Chuan-Fu Wang
CPC classification number: H01L45/1253 , H01L23/481 , H01L27/24 , H01L45/1666
Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.
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