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公开(公告)号：US12198036B2
公开(公告)日：2025-01-14
申请号：US17324062
申请日：2021-05-18
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.
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公开(公告)号：US12185554B2
公开(公告)日：2024-12-31
申请号：US17574422
申请日：2022-01-12
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Chi Shun Lin
IPC: H10B63/00 , G11C13/00 , H01L23/522 , H01L23/528 , H10N70/00
Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local source line, bit lines, and a shared source line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local source line extends in a column direction of the array area. The bit lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared source line is connected to the local source line. The shared source line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.
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公开(公告)号：US11594279B2
公开(公告)日：2023-02-28
申请号：US17367651
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.
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公开(公告)号：US11676662B2
公开(公告)日：2023-06-13
申请号：US17367641
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
CPC classification number: G11C13/0069 , G11C11/54 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0038
Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.
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公开(公告)号：US20220036947A1
公开(公告)日：2022-02-03
申请号：US17367651
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
IPC: G11C13/00
Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.
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Patent Agency Ranking
公开(公告)号：US20200227476A1
公开(公告)日：2020-07-16
申请号：US16666421
申请日：2019-10-29
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita
Abstract: The disclosure provides a resistance variable memory that can realize high integration. The resistance variable memory of the disclosure includes a plurality of transistors formed on a surface of a substrate, and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction. One electrode of each of the variable resistance elements is commonly electrically connected to one electrode of one transistor, and another electrode of each of the variable resistance elements is respectively electrically connected to a bit line, and another electrode of each of the transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.
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公开(公告)号：US20210390373A1
公开(公告)日：2021-12-16
申请号：US17324062
申请日：2021-05-18
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.
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公开(公告)号：US10943660B2
公开(公告)日：2021-03-09
申请号：US16801878
申请日：2020-02-26
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita
IPC: G11C13/00
Abstract: A resistive memory includes an array area where memory cells are arranged in rows and columns, word lines connected to the memory cells in a row direction, a local bit line extending in a column direction, local source lines, a shared bit line, and a writing device. Each memory cell includes a variable resistance element and an accessing transistor. The local source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line and second electrodes of the memory cells in the row direction. The writing device pre-charges the bit line and the source lines to a first voltage and applies a write pulse to the selected memory cell by discharging the corresponding selected source line after applying a write voltage to the selected word line, the writing device.
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公开(公告)号：US10395736B2
公开(公告)日：2019-08-27
申请号：US15953829
申请日：2018-04-16
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita
Abstract: A resistive random access memory with superior area efficiency and higher reliability is provided. The resistive random access memory RRAM in the present invention includes a memory array, which includes a plurality of memory cells MC arranged in rows and columns. Each memory cell MC includes a variable resistive element and an access transistor. Gates of the access transistors in a column are connected to a word line WL. First electrodes of the variable resistive element in a row are connected to a bit line BL. Second electrodes of the variable resistive element in the row are connected to a source line SL. The source line SL includes a local source line 250, which extends in a direction that is orthogonal to the bit lines BL0/BL1/BL2/BL3 and is shared by the bit lines BL0/BL1/BL2/BL3.
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公开(公告)号：US11983303B2
公开(公告)日：2024-05-14
申请号：US16392648
申请日：2019-04-24
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita
CPC classification number: G06F21/75 , G06F1/10 , H01L23/576
Abstract: The intrinsic data generation device of the disclosure includes a modulation control part outputting a modulation control signal for controlling modulation, a modulation part modulating a signal based on the modulation control signal and outputting a modulated modulation signal, a PUF circuit specifying a relationship between input data and output data based on random variation intrinsic to the device and changing the output data based on the modulation signal, a data holding part holding the output data from the PUF circuit in response to the modulation control signal, and an intrinsic data output part outputting intrinsic data based on the output data provided from the data holding part.
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