公开(公告)号：US20210057640A1

公开(公告)日：2021-02-25

申请号：US16991055

申请日：2020-08-12

Applicant: Winbond Electronics Corp.

Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

公开(公告)号：US12185553B2

公开(公告)日：2024-12-31

申请号：US17715065

申请日：2022-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Chih-Chao Huang ,  Ming-Che Lin ,  Frederick Chen ,  Han-Huei Hsu

IPC: H10B63/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H10N70/00

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

公开(公告)号：US20230329009A1

公开(公告)日：2023-10-12

申请号：US17715065

申请日：2022-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Chih-Chao Huang ,  Ming-Che Lin ,  Frederick Chen ,  Han-Huei Hsu

IPC: H01L27/24 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L29/0649 ,  H01L45/124 ,  H01L29/7851 ,  H01L45/16 ,  H01L29/66795

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

公开(公告)号：US20250072295A1

公开(公告)日：2025-02-27

申请号：US18945580

申请日：2024-11-13

Applicant: Winbond Electronics Corp.

Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

公开(公告)号：US20250072008A1

公开(公告)日：2025-02-27

申请号：US18939533

申请日：2024-11-07

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Chih-Chao Huang ,  Ming-Che Lin ,  Frederick Chen ,  Han-Huei Hsu

IPC: H10B63/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H10N70/00

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

公开(公告)号：US12193337B2

公开(公告)日：2025-01-07

申请号：US16991055

申请日：2020-08-12

Applicant: Winbond Electronics Corp.

Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.