公开(公告)号：US07894256B1

公开(公告)日：2011-02-22

申请号：US11881159

申请日：2007-07-25

Applicant: Farid Nemati ,  Scott Robins ,  Kevin J. Yang

Inventor： Farid Nemati ,  Scott Robins ,  Kevin J. Yang

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L29/66393 ,  H01L29/7436

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract translation: 新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。 可以在体硅晶片上制造包含这些存储单元的存储器阵列。 存储单元包含晶闸管体和栅极。 晶闸管体具有两个端部区域和两个基极区域，并且它设置在阱的顶部。 存储单元位于两个隔离区之间，并且隔离区延伸到阱的下方。 第一端区连接到字线，位线和第三线之一。 第二端区连接到字线，位线和第三线中的另一端。 门连接到字线，位线和第三行的剩余部分。

公开(公告)号：US20090086537A1

公开(公告)日：2009-04-02

申请号：US12232046

申请日：2008-09-10

Applicant: Makoto Kitagawa

Inventor： Makoto Kitagawa

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.

Abstract translation: 一种半导体器件，包括：具有晶闸管元件的存储单元，所述晶闸管元件具有形成在半导体衬底上的具有pnpn结构的栅极并具有第一和第二端子;以及存取晶体管，形成在所述半导体衬底上，并且具有连接到位的第一和第二端子 线路和晶闸管元件的第一端子，以及控制部分，其包括负载电流元件，其负载电流在读出操作时流向晶闸管元件的第二端子侧并被配置为对存储器执行访问控制 细胞。

公开(公告)号：US07460395B1

公开(公告)日：2008-12-02

申请号：US11159447

申请日：2005-06-22

Applicant: Hyun-Jin Cho ,  Farid Nemati

Inventor： Hyun-Jin Cho ,  Farid Nemati

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.

Abstract translation: 新的存储单元只能包含一个晶闸管。 不需要在电池中包括存取晶体管。 在一个实施例中，晶闸管是薄电容耦合晶闸管。 新的存储单元可以以多种方式连接到字，位和控制线，以形成不同的存储器阵列。 公开了字，位和控制线的时序和电压电平。

公开(公告)号：US20080239803A1

公开(公告)日：2008-10-02

申请号：US11692627

申请日：2007-03-28

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

Abstract translation: 提供了一种存储单元，其包括存取晶体管和门控侧栅晶体管（GLT）器件。 存取晶体管包括源节点。 门控侧向晶闸管（GLT）器件包括耦合到存取晶体管的源极节点的阳极节点。

公开(公告)号：US20050226067A1

公开(公告)日：2005-10-13

申请号：US11148530

申请日：2005-06-08

Applicant: S. Herner ,  Abhijit Bandyopadhyay

Inventor： S. Herner ,  Abhijit Bandyopadhyay

IPC: G11C7/00 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C29/00 ,  H01L21/336 ,  H01L21/82 ,  H01L27/24 ,  H01L29/73 ,  H01L45/00

CPC classification number: G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

Abstract: A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.

Abstract translation: 描述非易失性存储单元，存储单元包括半导体二极管。 构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。 编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。 在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。 电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。 描述了产生有利的未编程缺陷密度的制造技术。 本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

公开(公告)号：US5761134A

公开(公告)日：1998-06-02

申请号：US845246

申请日：1997-04-21

Applicant: Shinichi Masuda ,  Hiroshi Segawa

Inventor： Shinichi Masuda ,  Hiroshi Segawa

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C11/39

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106

Abstract: In a data reading circuit, an output signal from a sense amplifier which outputs a signal having a level corresponding to a potential difference between an input/output line pair is output through a first tri-state inverter and a second tri-state inverter. An NMOS transistor for precharging is provided between an output node of the first tri-state inverter and an output node (N3) of the sense amplifier. When the sense amplifier and the first tri-state inverter are inactivated, this transistor is also inactivated. As a result, an output node of the second tri-state inverter and an output node of the sense amplifier are connected with this transistor therebetween, so that the output node of the sense amplifier is precharged to an intermediate potential. According to the structure as described above, in the data reading circuit, a fast access is implemented, operation of the circuit is stabilized, and the lack of balance between the access times is suppressed.

Abstract translation: 在数据读取电路中，通过第一三态反相器和第二三态反相器输出输出具有与输入/输出线对之间的电位差相对应的电平的信号的读出放大器的输出信号。 用于预充电的NMOS晶体管设置在第一三态反相器的输出节点和读出放大器的输出节点（N3）之间。 当读出放大器和第一个三态反相器失活时，该晶体管也失活。 结果，第二三态反相器的输出节点和读出放大器的输出节点与其之间的晶体管连接，使得读出放大器的输出节点被预充电到中间电位。 根据如上所述的结构，在数据读取电路中，实现快速存取，电路的动作稳定，抑制了存取时间之间的平衡。

公开(公告)号：US5608250A

公开(公告)日：1997-03-04

申请号：US343016

申请日：1994-11-21

Applicant: Alexander Kalnitsky

Inventor： Alexander Kalnitsky

IPC: H01L21/8247 ,  G11C11/39 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: G11C11/39 ,  H01L29/792 ,  Y10S257/903 ,  Y10S438/91 ,  Y10S438/953

Abstract: A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

Abstract translation: 描述了在半导体衬底和绝缘栅场效应晶体管的栅极电介质层之间的界面处并入电子陷阱的半导体器件，该器件能够在电子陷阱中保持一定时间的电荷，从而允许易失性存储器电路 其中每个单元仅占用单个晶体管所需的面积。

公开(公告)号：US5065044A

公开(公告)日：1991-11-12

申请号：US426303

申请日：1989-10-24

Applicant: Kenichi Kasahara ,  Ichiro Ogura ,  Yoshiharu Tashiro

Inventor： Kenichi Kasahara ,  Ichiro Ogura ,  Yoshiharu Tashiro

IPC: G02F1/015 ,  G02F3/02 ,  G11C11/39 ,  H01L29/74 ,  H01L31/111 ,  H03K17/78 ,  H03K19/14

CPC classification number: G11C11/39 ,  Y10S359/90

Abstract: At least one electric pulse having a predetermined voltage which is higher than a switching voltage for a pnpn semiconductor device and a predetermined width is applied across the pnpn semiconductor device. The electric pulse width is set not to turn the pnpn semiconductor device on. Consequently, a predetermined amount of carriers are accumulated in the pnpn semiconductor device. In this circumstance, a trigger light is supplied to the pnpn semiconductor device to be turned on. As a result, an energy of the trigger light is largely decreased as compared to a conventional method.

公开(公告)号：US5023836A

公开(公告)日：1991-06-11

申请号：US381768

申请日：1989-07-18

Applicant: Toshihiko Mori

Inventor： Toshihiko Mori

IPC: G11C11/411 ,  G11C11/39 ,  H01L21/331 ,  H01L21/8229 ,  H01L21/8244 ,  H01L27/102 ,  H01L27/11 ,  H01L29/68 ,  H01L29/73 ,  H01L29/80

CPC classification number: B82Y10/00 ,  G11C11/39 ,  G11C2211/5614

Abstract: A semiconductor memory device comprises a transistor and a resistor. The transistor has negative differential resistance characteristics in an emitter current or a source current thereof. Therefore the semiconductor memory device has few elements and a simplified configuration, and thus high speed operation and large scale integration can be realized. Further, in the semiconductor memory device of the present invention, several variations in design are possible.

公开(公告)号：US4882706A

公开(公告)日：1989-11-21

申请号：US6720

申请日：1987-02-05

Applicant: Alan W. Sinclair

Inventor： Alan W. Sinclair

IPC: G11C11/411 ,  G11C8/04 ,  G11C8/12 ,  G11C11/39

CPC classification number: G11C11/39 ,  G11C8/04 ,  G11C8/12

Abstract: An electrical data storage element which provides for alteration of this stored data by way of a data line and address lines. Data is held as a charge set on a charge storage device. The state of the switch elements is sensed by way of the data line and address line.

Abstract translation: PCT No.PCT / GB86 / 00328 Sec。 371日期1987年2月5日 102（e）1987年2月5日PCT PCT 1986年6月9日PCT公布。 公开号WO86 / 07487 日期：1986年12月18日。一种电子数据存储元件，其通过数据线和地址线提供对该存储数据的改变。 数据作为在电荷存储装置上设定的电荷而保持。 通过数据线和地址线检测开关元件的状态。