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US5608250A Volatile memory cell with interface charge traps 失效
具有界面电荷陷阱的易失性存储单元

Volatile memory cell with interface charge traps
Abstract:
A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
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