公开(公告)号：US06385734B2

公开(公告)日：2002-05-07

申请号：US09801386

申请日：2001-03-08

Applicant: Lee Atkinson

Inventor： Lee Atkinson

IPC: G06F132

CPC classification number: G06F1/3221 ,  Y02D10/154

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract translation: 一种在允许CDROM驱动器继续播放音频CD的同时降低便携式计算机系统中的功耗的系统和方法。 当系统进入挂起模式时，检查CDROM驱动器的状态，如果播放音频CD，则它仍然通电，否则CDROM驱动器的电源也被挂起。 该系统识别音频CD何时完成播放，然后将CDROM驱动器置于挂起模式。

公开(公告)号：US06347377B2

公开(公告)日：2002-02-12

申请号：US09185674

申请日：1998-11-04

Applicant: Ronald Barbee

Inventor： Ronald Barbee

IPC: G06F132

CPC classification number: G06F1/3228 ,  G06F1/3203

Abstract: The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.

Abstract translation: 本发明是一种在基于处理器的系统中为电路提供电源管理装置的装置和方法。 该装置包括存储器，用于存储处理器系统被处理的指令序列和耦合到存储器的处理器。 存储的指令序列使得处理器：（a）确定电路的系统访问时间; （b）确定系统访问时间是否小于第一预定值，如果是，则增加电路的可访问性周期，在此期间电路处于活动状态。 描述各种实施例。

公开(公告)号：US06345362B1

公开(公告)日：2002-02-05

申请号：US09287173

申请日：1999-04-06

Applicant: Claude Louis Bertin ,  Alvar Antonio Dean ,  Kenneth Joseph Goodnow ,  Scott Whitney Gould ,  Wilbur David Pricer ,  William Robert Tonti ,  Sebastian Theodore Ventrone

Inventor： Claude Louis Bertin ,  Alvar Antonio Dean ,  Kenneth Joseph Goodnow ,  Scott Whitney Gould ,  Wilbur David Pricer ,  William Robert Tonti ,  Sebastian Theodore Ventrone

IPC: G06F132

CPC classification number: G06F9/3836 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/3867 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/171

Abstract: An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.

Abstract translation: 集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。 电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。 该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。 如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。

公开(公告)号：US06343363B1

公开(公告)日：2002-01-29

申请号：US09570155

申请日：2000-05-12

Applicant: Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

Inventor： Robert Maher ,  Raul A. Garibay, Jr. ,  Margaret R. Herubin ,  Mark Bluhm

IPC: G06F132

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3867 ,  G06F9/3869 ,  G06F13/4072 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.

Abstract translation: 在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。 处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路 和中断处理子电路。 响应于停止指令的执行，处理器（i）至少输入管道子电路而进入功率消耗降低的低功率操作模式，但不停止向中断处理子电路提供时钟信号，并且（ii ）向外部逻辑产生一个确认信号，指示管道子电路的时钟信号正在停止，从而进入低功率操作模式。 在优选实施例中，通过停止时钟发生器电路将时钟信号提供给管道子电路而不是中断处理子电路来进入低功率操作模式。 为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

公开(公告)号：US06330639B1

公开(公告)日：2001-12-11

申请号：US09342347

申请日：1999-06-29

Applicant: Blaise B. Fanning ,  Jeffrey R. Wilcox ,  Khong S. Foo

Inventor： Blaise B. Fanning ,  Jeffrey R. Wilcox ,  Khong S. Foo

IPC: G06F132

CPC classification number: G06F1/3275 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/14 ,  Y02D10/16

Abstract: The present invention provides a method, apparatus, and system for dynamically changing the sizes of power-control pools that are used to control the power consumption levels of memory devices. In one embodiment, a request to change the sizes of the memory power-control pools is received. In response to receiving the request to change the sizes of the memory power-control pools, the memory devices are placed in a specific operating mode or power state after being refreshed in a periodic refresh cycle. In response to a signal indicating that all memory devices have been placed in the specific operating mode, powercontrol pools are resized according to pool size values corresponding to the request received.

Abstract translation: 本发明提供一种用于动态地改变用于控制存储器件的功耗级别的功率控制池的大小的方法，装置和系统。 在一个实施例中，接收到改变存储器功率控制池的大小的请求。 响应于接收到改变存储器功率控制池的大小的请求，存储器件在周期性刷新周期中被刷新之后被置于特定的工作模式或功率状态。 响应于指示所有存储器件已经被置于特定操作模式的信号，功率控制池根据与所接收的请求对应的池大小值来调整大小。

公开(公告)号：US06327664B1

公开(公告)日：2001-12-04

申请号：US09302916

申请日：1999-04-30

Applicant: Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Christopher P. Miller

Inventor： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Christopher P. Miller

IPC: G06F132

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  Y02D10/13 ,  Y02D10/14

Abstract: An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.

Abstract translation: 提供了一种改进的存储器模块及其在计算机系统中的应用。 该模块包括DSP第一和第二可单独寻址的存储器芯片组。 第一组被配置为主要在信号处理元件的控制下起作用，并且第二存储体被配置为主要在系统存储器控制器的控制下起作用，尽管每个存储体的所有部分都可以由信号 处理元件和系统存储器控制器。 两个存储芯片组可以通过系统存储器控制器或DSP被置于至少一个较高功率状态和至少一个较低功率状态。 在较高功率状态下感测每个存储体的活动，并且相对于在较高功率状态的存储体的操作期间的任何活动来感测每个存储体的状况。 响应于每个银行的预选条件，可以通过信号处理元件或系统存储器控制器改变每个存储体的电源状态。 当从较低功率状态改变到较高功率状态时，每个存储体返回到预定的已知状态。 当分配给系统控制器的存储体被DSP置于另一状态时，这尤其重要。

公开(公告)号：US06282667B1

公开(公告)日：2001-08-28

申请号：US08953414

申请日：1997-10-17

Applicant: Ryu Nakazato

Inventor： Ryu Nakazato

IPC: G06F132

CPC classification number: G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  Y02D10/171 ,  Y02D50/20

Abstract: A sound controller comprises circuitry that performs a variety of sound functions. The circuitry is only powered when required by an application program. A power-saving driver receives a message issued from an operating system. When the message means indicates that a sound function is starting to be used, the power-saving driver turns on the power supply of a sound controller and then hands over the message to the sound device driver. In contrast, when the message indicates that the use of the sound function is ending, the power-saving driver first hands over the message to the sound driver, thereby causing the sound driver to execute an end process. After a predetermined time has elapsed since the power-saving driver handed over the message, it turns off the power supply of the sound controller.

Abstract translation: 声音控制器包括执行各种声音功能的电路。 电路仅在应用程序需要时供电。 省电驱动程序接收从操作系统发出的消息。 当消息装置指示开始使用声音功能时，节电驱动程序打开声音控制器的电源，然后将消息交给声音设备驱动程序。 相反，当消息指示使用声音功能结束时，节电驱动程序首先将消息转交给声音驱动器，从而使声音驱动程序执行结束处理。 在省电司机移交该消息经过预定时间后，关闭声控器的电源。

公开(公告)号：US06260150B1

公开(公告)日：2001-07-10

申请号：US09213102

申请日：1998-12-17

Applicant: Wilhelmus J. M. Diepstraten ,  Michael A. Fischer ,  Wesley D. Hardell

Inventor： Wilhelmus J. M. Diepstraten ,  Michael A. Fischer ,  Wesley D. Hardell

IPC: G06F132

CPC classification number: G06F9/485 ,  G06F9/461 ,  G06F9/5027 ,  G06F9/5094 ,  G06F9/542 ,  Y02D10/22 ,  Y02D10/24

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively, and (2) mode switching circuitry, coupled to the foreground and background task controllers, that places the processor in an idle state and a power saving mode when all of the contexts are inactive.

Abstract translation: 用于在处理器中管理多任务的上下文控制器及其操作方法。 在一个实施例中，上下文控制器包括：（1）分别将处理器资源分配给与前台和后台任务相对应的活动上下文的前台和后台任务控制器，以及耦合到前台和后台任务控制器的模式切换电路， 当所有上下文都不活动时，处理器处于空闲状态和省电模式。

公开(公告)号：US06259275B1

公开(公告)日：2001-07-10

申请号：US09562347

申请日：2000-05-01

Applicant: Valeriu Beiu

Inventor： Valeriu Beiu

IPC: G06F132

CPC classification number: H03K19/0813 ,  H03K19/0016

Abstract: A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two binary inputs adapted to receive corresponding input binary digits, the circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and at least one of the input binary digits and (2) a switch, coupled to the power down circuit, that interrupts DC current to at least a portion of the logic gate as a function of the power down signal.

Abstract translation: 降低逻辑门中的DC功耗的电路和方法，以及结合电路或方法的处理器。 在一个实施例中，其中逻辑门具有适于接收相应的输入二进制数字的至少两个二进制输入，该电路包括：（1）组合逻辑掉电电路，其根据输入数据信号产生掉电信号 以及至少一个输入二进制数字和（2）耦合到掉电电路的开关，其将作为功率下降信号的函数的DC电流中断到至少一部分逻辑门。

公开(公告)号：US06243821B1

公开(公告)日：2001-06-05

申请号：US09539588

申请日：2000-03-31

Applicant: Kenneth S. Reneris

Inventor： Kenneth S. Reneris

IPC: G06F132

CPC classification number: G06F1/3228 ,  G06F1/189 ,  G06F1/3203

Abstract: Waking a computer from a system state. A wake data structure enables a device to wake the computer from a sleeping state. The lowest system state is identified that allows selected devices to still wake the system based on the contents of the wake data structure for the device. A chosen device power state is selected for each of the devices within the computer system and each device is placed within their respective chosen device power state. Wake devices have a particular chosen device power state that supports that wake device's capability of waking the computer system. Other devices are typically turned off. Finally, the operating system turns off any of power resources within the computer system that are no longer used by any of the devices.

Abstract translation: 从系统状态唤醒计算机。 唤醒数据结构使设备能够将计算机从睡眠状态唤醒。 识别出最低的系统状态，允许所选择的设备基于设备的唤醒数据结构的内容来仍然唤醒系统。 为计算机系统内的每个设备选择所选择的设备电源状态，并且将每个设备放置在其各自选择的设备电源状态内。 唤醒设备具有特定的选择的设备电源状态，其支持唤醒设备唤醒计算机系统的能力。 其他设备通常关闭。 最后，操作系统关闭计算机系统中不再被任何设备使用的任何电源。