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    Field programmable memory array
    1.
    发明授权
    Field programmable memory array 失效
    现场可编程存储阵列

    公开(公告)号：US06233191B1

    公开(公告)日：2001-05-15

    申请号：US09510326

    申请日：2000-02-22

    Applicant: Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

    Inventor： Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

    IPC: G11C700

    CPC classification number: G06F7/785 ,  G06F5/10 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C8/00 ,  H03K19/17704 ,  H03K19/1776

    Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

    Abstract translation: 提供具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

    Programmable logic cell
    3.
    发明授权
    Programmable logic cell 失效
    可编程逻辑单元

    公开(公告)号：US5748009A

    公开(公告)日：1998-05-05

    申请号：US707840

    申请日：1996-09-09

    Applicant: Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    Inventor： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/1737

    Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

    Abstract translation: 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 优选的编程方法利用用户编程的SRAM存储单元。

    Programmable array interconnect latch
    4.
    发明授权
    Programmable array interconnect latch 失效
    可编程阵列互连锁存器

    公开(公告)号：US5732246A

    公开(公告)日：1998-03-24

    申请号：US480639

    申请日：1995-06-07

    Applicant: Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

    Inventor： Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

    IPC: H03K19/173 ,  G01R31/3185 ,  H03K3/037 ,  H03K19/177 ,  G06F9/455 ,  G06F17/50

    CPC classification number: G01R31/318519 ,  H03K19/17704 ,  H03K19/17748 ,  H03K3/0375

    Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.

    Abstract translation: 可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。 可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。 选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。 信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。 在另一实施例中，信号存储电路包括LSSD寄存器。 根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。 每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。 在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。 在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。

    Programmable inverter circuit used in a programmable logic cell
    7.
    发明授权
    Programmable inverter circuit used in a programmable logic cell 失效
    可编程逻辑单元中使用的可编程逆变器电路

    公开(公告)号：US5781032A

    公开(公告)日：1998-07-14

    申请号：US707839

    申请日：1996-09-09

    Applicant: Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    Inventor： Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    IPC: H03K19/177 ,  H03K7/38 ,  H03K19/21

    CPC classification number: H03K19/1778 ,  H03K19/17728

    Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

    Abstract translation: 可编程逻辑单元具有四个单元输入节点和多个组合逻辑电路。 提供四个逆变器电路用于可编程地反相各个输入逻辑信号，每个反相器电路具有连接到各个单元输入节点的反相器输入节点，用于从其接收其相应的输入逻辑信号。 每个逆变器可编程为第一状态，其中表示输入逻辑信号的补码的逻辑信号被提供给逆变器输出节点，并且第二状态，其中表示输入逻辑信号的非补码的逻辑信号被提供给 逆变器输出节点。 逆变器电路在第一和第二状态下缓冲它们的输入逻辑信号。 多个组合逻辑电路的第一逻辑门具有第一和第二输入，每个连接到四个反相器电路中的两个中的一个的相应输出节点，第二逻辑门具有第一和第二输入，每个连接到相应的输出节点 的四个逆变器电路中的另外两个之一。 逆变器电路可以被实现为XNOR门。

    Function generator for programmable gate array
    8.
    发明授权
    Function generator for programmable gate array 失效
    可编程门阵列功能发生器

    公开(公告)号：US5760611A

    公开(公告)日：1998-06-02

    申请号：US739102

    申请日：1996-10-25

    Applicant: Scott Whitney Gould

    Inventor： Scott Whitney Gould

    IPC: H03K19/177

    CPC classification number: H03K19/1778 ,  H03K19/17704 ,  H03K19/17728

    Abstract: A programmable logic circuit provides a variety of logic functions including AND/NAND, OR/NOR, XOR/XNOR. Selection of logic function is provided by controlling inputs, using programmable inverters and programmable multiplexers. The logic circuit can be incorporated into a field programmable gate array.

    Abstract translation: 可编程逻辑电路提供包括AND / NAND，OR / NOR，XOR / XNOR在内的各种逻辑功能。 通过控制输入，使用可编程逆变器和可编程多路复用器来提供逻辑功能的选择。 逻辑电路可以并入现场可编程门阵列中。

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