公开(公告)号：US20100269012A1

公开(公告)日：2010-10-21

申请号：US12827414

申请日：2010-06-30

Applicant: Bruce G. Hazelzet

Inventor： Bruce G. Hazelzet

IPC: H03M13/00 ,  G06F11/16 ,  G06F1/32

CPC classification number: H03M13/19 ,  G06F11/1044

Abstract: An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices.

Abstract translation: 增强的四级使能缓冲器设备，其包括用于接收输入数据的输入端口，该输入数据包括指向多达四级存储器设备中的一个或多个的地址和命令数据。 缓冲装置还包括用于驱动地址和命令数据中的一个或多个的一个或多个缓冲器电路，用于在多达四个等级的存储器件之间进行选择的多个芯片选择输入线以及多个芯片选择输出线，用于 访问最多四个内存设备。 缓冲装置还包括一个省电装置，用于当相应的片选输入线不活动时使一个或多个缓冲电路处于非活动模式。 缓冲设备可操作以访问多达四级的存储设备。

公开(公告)号：US20080098277A1

公开(公告)日：2008-04-24

申请号：US11551866

申请日：2006-10-23

Applicant: Bruce G. Hazelzet

Inventor： Bruce G. Hazelzet

IPC: H03M13/00

CPC classification number: H03M13/19 ,  G06F11/1044

Abstract: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module. The memory module also includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

Abstract translation: 具有电源门控和容错地址和命令总线的高密度高可靠性存储器模块。 存储器模块包括具有第一侧和第二侧的矩形印刷电路板，长度在149和153毫米之间，第一和第二端的宽度小于所述长度。 存储器模块还包括沿着所述板的第一边缘延伸的第一多个连接器位置，所述第一边缘延伸板的长度，并且在第二侧上延伸的第二多个连接器位置延伸在所述板的所述第一边缘上。 存储器模块还包括与电路板通信的缓冲设备，用于访问最多四个安装在电路板的第一侧和第二侧的存储器件。 此外，包括功率节省装置，用于使缓冲器装置的全部或一部分响应于存储器模块上的当前活动而处于非活动模式。 存储器模块还包括定位键，其定位键位于所述第一边缘上并且位于距所述卡的所述第一端82mm和86mm之间并位于距所述卡的所述第二端66至70mm之间。

公开(公告)号：US06349390B1

公开(公告)日：2002-02-19

申请号：US09224990

申请日：1999-01-04

Applicant: Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg

Inventor： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg

IPC: G06F1110

CPC classification number: G06F11/106

Abstract: A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.

Abstract translation: 提供了一种用于附接到具有存储器总线的计算机系统的存储器模块，以及通过擦除模块上的软错误来使用存储器模块进行纠错的方法。 该模块包括在卡上具有存储器存储芯片的印刷电路卡，以存储数据位和相关联的ECC校验位。 在电路卡上提供标签以将该卡耦合到计算机系统的存储器总线。 逻辑电路选择性地操作地连接和断开存储器芯片和存储器总线。 信号处理器与存储器芯片以电路关系连接。 逻辑电路选择性地允许信号处理器从存储器芯片读取存储的数据位和相关的校验位，从读取的存储的数据位重新计算校验位，将重新计算的校验位与存储的校验位进行比较，校正所有至少一个 存储数据位和存储的相关检查位中的位错误并且将存储器芯片中的正确数据位和相关联的校验位重新存储。 当存储器芯片和存储器总线断开时，在存储数据位和校验位期间发生的单位软错误在数据从读存储器芯片读取到数据总线之前被周期性地校正。

公开(公告)号：US06233639B1

公开(公告)日：2001-05-15

申请号：US09225524

申请日：1999-01-04

Applicant: Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

Inventor： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

IPC: G06F1300

CPC classification number: G11C5/066

Abstract: A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

Abstract translation: 在具有DSP和存储器总线控制器的存储卡上提供串行总线和通过系统存储器控制器与计算机系统上的设备的连接，以允许存储卡上的DSP访问系统设备而不使用系统 内存总线 串行总线是通过系统存储器控制器将设备连接到DSP的双线串行总线。 如果多个存储卡存在于DSP或多于一个设备正在争取访问，则系统存储器控制器或仲裁每个存储卡或竞争设备的访问。 在这种情况下，当串行总线想要访问特定设备时，串行总线将向系统存储器控制器发信号通知，并且系统存储器控制器将充当仲裁器以授予或不授予对请求访问的特定存储卡或设备的访问权限。 如果访问被授予，总线存储器控制器在串行总线上输出所需的控制或命令字，然后输出地址和所需的数据。 该串行信息由系统存储器控制器接收，该系统存储器控制器对其进行分组，并且在完成时，在并行总线上快速地输出信息，例如， PCI总线到需要信息的设备。

公开(公告)号：US06467053B1

公开(公告)日：2002-10-15

申请号：US09340804

申请日：1999-06-28

Applicant: Brian J. Connolly ,  Steven A. Grundon ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  James R. Mallabar

Inventor： Brian J. Connolly ,  Steven A. Grundon ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  James R. Mallabar

IPC: G06F11277

CPC classification number: G11C29/56 ,  G11C29/56012 ,  G11C2029/5602

Abstract: A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.

Abstract translation: 同步DRAM存储器测试组件，其将具有同步总线的普通PC或工作站转换为存储器测试器。 测试组件可以分为两个部分：诊断卡和适配卡，以限制系统插座上的机械负载以及允许变化的外形尺寸。 该测试组件架构支持66 MHz及以上的内存总线速度，并为逻辑分析仪提供方便的访问。 测试组件支持注册和非缓冲同步DRAM产品。 测试组件允许使用外部逻辑分析仪比较好的和有问题的同步模块。 它允许解决在系统环境中唯一发生的系统内故障，并且可能难以或不可能复制。 测试组件使用锁相环（PLL）缓冲区将系统时钟重新驱动到测试组件上的存储器模块插槽，以允许定时调整，以最大限度地减少系统的存储器总线时序由于额外的电线长度和负载而的劣化。 测试组件可编程为适应变化的总线时序，例如：CAS（列地址选通）延迟和突发长度变化。 它设计有现场可编程门阵列（FPGA），可在内部进行更改，无需修改测试组件。

公开(公告)号：US06457155B1

公开(公告)日：2002-09-24

申请号：US09465609

申请日：1999-12-17

Applicant: Timothy J. Dell ,  Kent A. Dramstad ,  Marc R. Faucher ,  Bruce G. Hazelzet

Inventor： Timothy J. Dell ,  Kent A. Dramstad ,  Marc R. Faucher ,  Bruce G. Hazelzet

IPC: G11C2900

CPC classification number: G11C5/02 ,  G06F11/10 ,  G11C5/04 ,  G11C2029/0411

Abstract: A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of. a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.

Abstract translation: 提供了一种存储卡适配器和方法，其可以向计算机系统的存储器模块添加功能或提供功能，而无需更换和丢弃现有的存储器模块。 提供了一种适配器，其具有能够插入到存储器模块接收插座中的电触点。 主板和存储模块接收插座，能够接收和保持诸如SIMM的存储器模块。 该适配器具有逻辑，电路和/或存储器芯片，以便为现有存储器模块增加新功能，并且还具有与计算机系统的主板正确接口所需的所有信息和硬件。 本发明可以在SIMM上添加诸如奇偶校验，纠错码和纠错码的各种功能，以及从系统中形成的用于在SIMM上使用的信号的转换信号，其中由计算机生成的形式的信号与 SIMM。

公开(公告)号：US07870459B2

公开(公告)日：2011-01-11

申请号：US11551866

申请日：2006-10-23

Applicant: Bruce G. Hazelzet

Inventor： Bruce G. Hazelzet

IPC: H03M13/00

CPC classification number: H03M13/19 ,  G06F11/1044

Abstract: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module. The memory module also includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

Abstract translation: 具有电源门控和容错地址和命令总线的高密度高可靠性存储器模块。 存储器模块包括具有第一侧和第二侧的矩形印刷电路板，长度在149和153毫米之间，第一和第二端的宽度小于所述长度。 存储器模块还包括沿着所述板的第一边缘延伸的第一多个连接器位置，所述第一边缘延伸板的长度，并且在第二侧上延伸的第二多个连接器位置延伸在所述板的所述第一边缘上。 存储器模块还包括与电路板通信的缓冲设备，用于访问最多四个安装在电路板的第一侧和第二侧的存储器件。 此外，包括功率节省装置，用于使缓冲器装置的全部或一部分响应于存储器模块上的当前活动而处于非活动模式。 存储器模块还包括定位键，其定位键位于所述第一边缘上并且位于距所述卡的所述第一端82mm和86mm之间并位于距所述卡的所述第二端66至70mm之间。

公开(公告)号：US07646649B2

公开(公告)日：2010-01-12

申请号：US10707053

申请日：2003-11-18

Applicant: Bruce G. Hazelzet ,  Mark W. Kellogg ,  Darcie J. Rankin

Inventor： Bruce G. Hazelzet ,  Mark W. Kellogg ,  Darcie J. Rankin

IPC: G11C11/00

CPC classification number: G06F13/4243 ,  G11C7/1078 ,  G11C7/109

Abstract: A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

Abstract translation: 具有选择性地提供非反相或反相信号的多个DRAM的存储器系统。 DRAM具有从同时驱动多个信号的寄存器接受非反相或反相地址/命令信号的能力。 该系统包括具有可编程输入极性的DRAM接收器和具有可编程输出极性的寄存器。

公开(公告)号：US07477522B2

公开(公告)日：2009-01-13

申请号：US11551913

申请日：2006-10-23

Applicant: Bruce G. Hazelzet

Inventor： Bruce G. Hazelzet

IPC: H05K7/00

CPC classification number: H05K1/117 ,  G11C5/04 ,  H05K1/181 ,  H05K2201/09145 ,  H05K2203/167

Abstract: A high density high reliability memory module with a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes one or more buffer devices in communication with the circuit board for accessing one or more of the four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, the memory module includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

Abstract translation: 具有容错地址和命令总线的高密度高可靠性存储器模块。 存储器模块包括具有第一侧和第二侧的矩形印刷电路板，长度在149和153毫米之间，第一和第二端的宽度小于所述长度。 存储器模块还包括沿着所述板的第一边缘延伸的第一多个连接器位置，所述第一边缘延伸板的长度，并且在第二侧上延伸的第二多个连接器位置延伸在所述板的所述第一边缘上。 存储器模块还包括与电路板通信的一个或多个缓冲器装置，用于访问安装在电路板的第一侧和第二侧的四个等级的存储器件中的一个或多个。 此外，存储器模块包括定位键，其定位键位于所述第一边缘上并且位于距所述卡的所述第一端82mm和86mm之间并位于距所述卡的所述第二端66至70mm之间。

公开(公告)号：US06327664B1

公开(公告)日：2001-12-04

申请号：US09302916

申请日：1999-04-30

Applicant: Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Christopher P. Miller

Inventor： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Christopher P. Miller

IPC: G06F132

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  Y02D10/13 ,  Y02D10/14

Abstract: An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.

Abstract translation: 提供了一种改进的存储器模块及其在计算机系统中的应用。 该模块包括DSP第一和第二可单独寻址的存储器芯片组。 第一组被配置为主要在信号处理元件的控制下起作用，并且第二存储体被配置为主要在系统存储器控制器的控制下起作用，尽管每个存储体的所有部分都可以由信号 处理元件和系统存储器控制器。 两个存储芯片组可以通过系统存储器控制器或DSP被置于至少一个较高功率状态和至少一个较低功率状态。 在较高功率状态下感测每个存储体的活动，并且相对于在较高功率状态的存储体的操作期间的任何活动来感测每个存储体的状况。 响应于每个银行的预选条件，可以通过信号处理元件或系统存储器控制器改变每个存储体的电源状态。 当从较低功率状态改变到较高功率状态时，每个存储体返回到预定的已知状态。 当分配给系统控制器的存储体被DSP置于另一状态时，这尤其重要。