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    Analogue-to-digital converter
    21.
    发明授权
    Analogue-to-digital converter 有权

    公开(公告)号：US09923574B2

    公开(公告)日：2018-03-20

    申请号：US15663411

    申请日：2017-07-28

    申请人： Cirrus Logic International Semiconductor Ltd.

    发明人： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

    IPC分类号： H03M7/30 ,  H03M1/18 ,  H03M1/50 ,  H03M3/00 ,  H03K7/08 ,  H03K9/08

    CPC分类号： H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

    摘要： This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

    METHOD AND ARRANGEMENT FOR SETTING AN EFFECTIVE RESOLUTION OF AN OUTPUT SIGNAL IN INCREMENTAL DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS
    22.
    发明申请
    METHOD AND ARRANGEMENT FOR SETTING AN EFFECTIVE RESOLUTION OF AN OUTPUT SIGNAL IN INCREMENTAL DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS 有权
    用于设置输入信号在增量型三角形模拟数字转换器中的有效分辨率的方法和布置

    公开(公告)号：US20160142072A1

    公开(公告)日：2016-05-19

    申请号：US14939679

    申请日：2015-11-12

    申请人： ZENTRUM MIKROELEKTRONIK DRESDEN AG

    发明人： Raik RICHTER ,  Marko MAILAND

    IPC分类号： H03M3/00

    CPC分类号： H03M3/464 ,  H03M3/356 ,  H03M3/39 ,  H03M3/484 ,  H03M3/488

    摘要： A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.

    摘要翻译： 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。

    Analog to Digital Conversion
    24.
    发明申请
    Analog to Digital Conversion 有权
    模数转换

    公开(公告)号：US20130271303A1

    公开(公告)日：2013-10-17

    申请号：US13878331

    申请日：2011-10-25

    申请人： Francesco Rizzo ,  Shyam Somayajula

    发明人： Francesco Rizzo ,  Shyam Somayajula

    IPC分类号： H03M3/00

    CPC分类号： H03M3/458 ,  H03G1/0035 ,  H03G1/0094 ,  H03M3/484

    摘要： A delta-sigma analog-to-digital converter comprises: a summing stage having a first input for an input signal and a second input for a feedback signal; an integrator coupled to an output of the summing stage; an analog-to-digital conversion stage coupled to an output of the integrator; and a switchable gain stage coupled in a feedback path between an output of the analog-to-digital conversion stage and the second input of the summing stage. The switchable gain stage is arranged to switch, responsive to a gain selection signal, between a first gain and a second gain via a transition period comprising time periods during which the switchable gain stage has the first gain interleaved with time periods during which the switchable gain stage has the second gain. The time periods at the first gain comprise periods that decrease in duration over the transition period and the time periods at the second gain comprise periods that increase in duration over the transition period.

    摘要翻译： Δ-Σ模数转换器包括：加法级，其具有用于输入信号的第一输入和用于反馈信号的第二输入; 耦合到所述求和级的输出的积分器; 耦合到积分器的输出的模数转换级; 以及耦合在模数转换级的输出和求和级的第二输入之间的反馈路径中的可切换增益级。 可切换增益级被布置成经由包括时间周期的转换周期在第一增益和第二增益之间响应于增益选择信号而切换，在此期间可切换增益级具有第一增益，该时间周期与可切换增益 阶段有第二个增益。 第一增益的时间段包括在过渡期间内持续时间减少的周期，而在第二增益期间的时间周期包括在过渡周期内持续时间增加的周期。

    Input converter for a hearing aid and signal conversion method
    25.
    发明授权
    Input converter for a hearing aid and signal conversion method 有权
    用于助听器和信号转换方法的输入转换器

    公开(公告)号：US08493256B2

    公开(公告)日：2013-07-23

    申请号：US13242719

    申请日：2011-09-23

    申请人： Niels Ole Knudsen

    发明人： Niels Ole Knudsen

    IPC分类号： H03M3/02 ,  H03M1/12

    CPC分类号： H03M1/002 ,  H03M1/12 ,  H03M3/43 ,  H03M3/458 ,  H03M3/484 ,  H03M3/486 ,  H04R25/505

    摘要： In order to minimize noise and current consumption in a hearing aid, an input converter comprising a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.

    摘要翻译： 为了最小化助听器中的噪声和电流消耗，设计了一种包括第一电压互感器和用于助听器的delta-sigma类型的模 - 数转换器的输入转换器。 输入转换器的模数转换器具有输入级，输出级和反馈回路，输入级包括放大器（QA）和积分器（RLF）。 第一变压器（IT）具有变压比，使得它提供大于输入电压的输出电压，并被放置在输入转换器的上游输入级。 具有变压比使得其提供大于输入电压的输出电压的第二变压器（OT）可选地放置在转换器的反馈环路中。 电压互感器（IT，OT）是开关电容器电压互感器，每个变压器（IT，OT）具有至少两个电容器（Ca，Cb，Cc，Cd）。 本发明还提供一种转换模拟信号的方法。

    Gain matching method and system for single bit gain ranging analog-to-digital converter
    27.
    发明申请
    Gain matching method and system for single bit gain ranging analog-to-digital converter 有权
    单比特增益测距模数转换器的增益匹配方法和系统

    公开(公告)号：US20090140897A1

    公开(公告)日：2009-06-04

    申请号：US11998618

    申请日：2007-11-30

    申请人： John Healy ,  Colin Lyden

    发明人： John Healy ,  Colin Lyden

    IPC分类号： H03M1/06

    CPC分类号： H03M3/484 ,  H03M3/338 ,  H03M3/434

    摘要： A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

    摘要翻译： 一种用于单位增益测距模数转换器的增益匹配方法，包括响应于增益设置，选择在模拟输入和模数转换器之间互连的多元件增益控制阵列中使能的增益元件数量 转换器，并且在增益元件中对选定数量的增益元件的启用进行构图，以便在转换器的增益设置的范围内匹配模数转换器的增益，以减少由于增益元件失配引起的带内增益误差。

    SIGMA DELTA MODULATOR
    28.
    发明申请
    SIGMA DELTA MODULATOR 有权
    SIGMA DELTA调制器

    公开(公告)号：US20090066549A1

    公开(公告)日：2009-03-12

    申请号：US10599343

    申请日：2005-04-11

    申请人： Henrik Thomsen ,  Claus Erdmann Fuerst

    发明人： Henrik Thomsen ,  Claus Erdmann Fuerst

    IPC分类号： H03M3/00

    CPC分类号： H03M3/484 ,  H03M3/45 ,  H03M3/454 ,  H03M3/482 ,  H03M3/49 ,  H03M3/492

    摘要： A method of controlling a sigma delta modulator with a loop which establishes a signal transfer function, STF, and a quantization noise transfer function, NTF, of the sigma delta modulator, wherein the sigma delta modulator receives an input signal, x(n), and provides a modulated output signal, y(n) in response to the input signal. The method is characterized in comprising the step of controlling the sigma delta modulator to change the quantization noise transfer function, NTF, in response to a signal feature, A(n), which is correlated with the input signal.

    摘要翻译： 一种利用建立Σ-Δ调制器的信号传递函数STF和量化噪声传递函数NTF的环路来控制Σ-Δ调制器的方法，其中Σ-Δ调制器接收输入信号x（n） 并且响应于输入信号提供调制输出信号y（n）。 该方法的特征在于包括响应于与输入信号相关的信号特征A（n），控制Σ-Δ调制器改变量化噪声传递函数NTF的步骤。

    SIGMA DELTA MODULATOR AND RELATED METHOD THEREOF
    29.
    发明申请
    SIGMA DELTA MODULATOR AND RELATED METHOD THEREOF 有权
    SIGMA DELTA调制器及其相关方法

    公开(公告)号：US20090033533A1

    公开(公告)日：2009-02-05

    申请号：US12179556

    申请日：2008-07-24

    申请人： Hung-Chuan Pai ,  Chao-Tung Yang

    发明人： Hung-Chuan Pai ,  Chao-Tung Yang

    IPC分类号： H03M3/02

    CPC分类号： H03M3/484 ,  H03M3/43 ,  H03M3/49

    摘要： A sigma-delta modulator includes a loop filter, a single bit quantizer, a single bit DAC, an adder. The loop filter is for filtering a summed signal to generate a filtered signal. The single bit quantizer is coupled to the loop filter, for performing a quantization process to the filtered signal to generate a quantized signal. The single bit DAC is coupled to the single bit quantizer, has an adjustable configuration, and is for generating a feedback signal according to the quantized signal and the configuration thereof. The adder is coupled to the loop filter and the single bit DAC, for summing an input signal and the feedback signal to generate the summed signal.

    摘要翻译： Σ-Δ调制器包括环路滤波器，单比特量化器，单比特DAC，加法器。 环路滤波器用于滤波求和信号以产生滤波信号。 单位量化器耦合到环路滤波器，用于对经滤波的信号执行量化处理以产生量化信号。 单位DAC耦合到单位量化器，具有可调配置，并且用于根据量化信号及其配置产生反馈信号。 加法器耦合到环路滤波器和单位DAC，用于对输入信号和反馈信号求和以产生求和信号。