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公开(公告)号：US08890734B2
公开(公告)日：2014-11-18
申请号：US13878331
申请日：2011-10-25
申请人： Francesco Rizzo , Shyam Somayajula
发明人： Francesco Rizzo , Shyam Somayajula
CPC分类号： H03M3/458 , H03G1/0035 , H03G1/0094 , H03M3/484
摘要： A delta-sigma analog-to-digital converter includes: a summing stage having a first input for an input signal and a second input for a feedback signal; an integrator coupled to an output of the summing stage; an analog-to-digital conversion stage coupled to an output of the integrator; and a switchable gain stage coupled in a feedback path between an output of the analog-to-digital conversion stage and the second input of the summing stage. The switchable gain stage is arranged to switch, responsive to a gain selection signal, between a first gain and a second gain via a transition period comprising time periods during which the switchable gain stage has the first gain interleaved with time periods during which the switchable gain stage has the second gain.
摘要翻译： Δ-Σ模数转换器包括：加法级，其具有用于输入信号的第一输入和用于反馈信号的第二输入; 耦合到所述求和级的输出的积分器; 耦合到积分器的输出的模数转换级; 以及耦合在模数转换级的输出和求和级的第二输入之间的反馈路径中的可切换增益级。 可切换增益级被布置为经由包括时间周期的转换周期的第一增益和第二增益之间的响应于增益选择信号而切换，在该时间段期间，可切换增益级具有第一增益，其中可切换增益 阶段有第二个增益。
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公开(公告)号：US20130271303A1
公开(公告)日：2013-10-17
申请号：US13878331
申请日：2011-10-25
申请人： Francesco Rizzo , Shyam Somayajula
发明人： Francesco Rizzo , Shyam Somayajula
IPC分类号： H03M3/00
CPC分类号： H03M3/458 , H03G1/0035 , H03G1/0094 , H03M3/484
摘要： A delta-sigma analog-to-digital converter comprises: a summing stage having a first input for an input signal and a second input for a feedback signal; an integrator coupled to an output of the summing stage; an analog-to-digital conversion stage coupled to an output of the integrator; and a switchable gain stage coupled in a feedback path between an output of the analog-to-digital conversion stage and the second input of the summing stage. The switchable gain stage is arranged to switch, responsive to a gain selection signal, between a first gain and a second gain via a transition period comprising time periods during which the switchable gain stage has the first gain interleaved with time periods during which the switchable gain stage has the second gain. The time periods at the first gain comprise periods that decrease in duration over the transition period and the time periods at the second gain comprise periods that increase in duration over the transition period.
摘要翻译： Δ-Σ模数转换器包括：加法级，其具有用于输入信号的第一输入和用于反馈信号的第二输入; 耦合到所述求和级的输出的积分器; 耦合到积分器的输出的模数转换级; 以及耦合在模数转换级的输出和求和级的第二输入之间的反馈路径中的可切换增益级。 可切换增益级被布置成经由包括时间周期的转换周期在第一增益和第二增益之间响应于增益选择信号而切换，在此期间可切换增益级具有第一增益，该时间周期与可切换增益 阶段有第二个增益。 第一增益的时间段包括在过渡期间内持续时间减少的周期，而在第二增益期间的时间周期包括在过渡周期内持续时间增加的周期。
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公开(公告)号：US20120306502A1
公开(公告)日：2012-12-06
申请号：US13516578
申请日：2010-12-10
CPC分类号： G01R31/024 , G01R31/2635 , H05B33/0893
摘要： The present invention discloses a current controlling circuit wherein the circuit (200) comprises a DC power source (202), an inductor (204), a N-channel Metal Oxide Semiconductor (NMOS) (206), one or more LEDs (208) connected in series, a first resistor (Rsense) and a switching arrangement (210). The positive terminal of the DC power source (202) is connected to the inductor (204) in series. The series of LED (208) is connected in series with the inductor (204) and the first resistor (Rsense). According to an embodiment the switching arrangement (210) comprises a second resistor (Rslt), a first switch (212) and a second switch (214). The second resistor (Rslt) is connected in series with the second switch (214) and connected in parallel with the first switch (212). The switching arrangement (210) is connected in series with the first resistor (Rsense) and the negative terminal of the DC supply (202).
摘要翻译： 本发明公开了一种电流控制电路，其中电路（200）包括直流电源（202），电感器（204），N沟道金属氧化物半导体（NMOS）（206），一个或多个LED（208） 串联连接，第一电阻（Rsense）和开关装置（210）。 直流电源（202）的正极端子与电感器（204）串联连接。 LED（208）系列与电感器（204）和第一电阻器（Rsense）串联连接。 根据实施例，开关装置（210）包括第二电阻器（Rslt），第一开关（212）和第二开关（214）。 第二电阻器（Rslt）与第二开关（214）串联连接并与第一开关（212）并联连接。 开关装置（210）与DC电源（202）的第一电阻（Rsense）和负极端子串联连接。
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4.发明授权公开(公告)号：US07324162B2
公开(公告)日：2008-01-29
申请号：US10964550
申请日：2004-10-13
IPC分类号： H03M1/12
摘要： A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.
摘要翻译： 一种视频解码器，其中1）对于给定位计数模数转换器可以改进分辨率质量，2）可以使用具有基本相似质量的较低位计数模数转换器，或3）改进的组合 可以进行低位数模数转换器的分辨率质量。 在优选实施例中，在已经接收到合成信号的同步部分之后并且在接收到活动视频之前，将DC偏压添加到视频信号。 然后在活动视频周期结束后删除该偏置。 通过施加该偏压，视频信号的直流电压电平实际上被减小，从而也可以减小模数转换处理的满量程值。 因此，与使用无偏信号相比，获得了增加的A / D转换器分辨率。 在替代实施例中，同步部分可以在前部门口向上偏置，然后在后廊期间返回。
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公开(公告)号：US08912798B2
公开(公告)日：2014-12-16
申请号：US13516578
申请日：2010-12-10
CPC分类号： G01R31/024 , G01R31/2635 , H05B33/0893
摘要： A current controlling circuit comprises a DC power source, an inductor, a N-channel Metal Oxide Semiconductor (NMOS), one or more LEDs connected in series, a first resistor and a switching arrangement. The positive terminal of the DC power source is connected to the inductor in series. The series of LED is connected in series with the inductor and the first resistor. According to an embodiment the switching arrangement comprises a second resistor, a first switch and a second switch. The second resistor is connected in series with the second switch and connected in parallel with the first switch. The switching arrangement is connected in series with the first resistor and the negative terminal of the DC supply.
摘要翻译： 电流控制电路包括直流电源，电感器，N沟道金属氧化物半导体（NMOS），串联连接的一个或多个LED，第一电阻器和开关装置。 直流电源的正极端子与电感器串联连接。 该系列LED与电感和第一个电阻串联。 根据实施例，开关装置包括第二电阻器，第一开关和第二开关。 第二电阻器与第二开关串联连接并与第一开关并联连接。 开关装置与DC电源的第一电阻器和负极端子串联。
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公开(公告)号：US08787597B2
公开(公告)日：2014-07-22
申请号：US12713078
申请日：2010-02-25
IPC分类号： H04R3/00
CPC分类号： H04R3/002 , G10K11/002 , H04R3/00 , H04R3/007
摘要： Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.
摘要翻译： 公开了用于抑制音频信号中的弹出噪声的系统和方法。 该系统包括由引脚接口和互补引脚接口共享的驱动器电路。 控制单元耦合到引脚接口和互补引脚接口。 要激活引脚接口，控制单元配置为首先在互补引脚接口处激活驱动器输出。 一旦互补引脚接口达到预设电压，驱动器输出就由控制单元切换到引脚接口。 此外，可以通过重新使用在引脚接口处计算出的校准数据，在互补引脚接口上校准驱动器电路的直流偏移。 此外，可以基于驱动器电路的校准数据从预偏置电路提供直流校正信号。
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公开(公告)号：US20070188358A1
公开(公告)日：2007-08-16
申请号：US11738745
申请日：2007-04-23
申请人： Shyam Somayajula
发明人： Shyam Somayajula
IPC分类号： H03M7/34
CPC分类号： H03M1/0658 , H03M1/0818 , H03M1/1215 , H03M1/128 , H03M3/336 , H03M3/458 , H03M3/47
摘要： A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.
摘要翻译： 一种系统包括可由具有相关时钟周期的数字时钟信号来计时的数字电路。 该系统还包括耦合到采样电路的采样时钟产生电路。 采样时钟产生电路可以被配置为接收相对于数字时钟信号具有固定相位关系的输入时钟。 采样时钟产生电路还可以产生具有与时钟周期内的第一相对偏移相对应的第一采样边沿和对应于时钟周期内的不同相对偏移的后续采样边沿的采样时钟。 采样电路可以被配置为在对应于第一采样边缘的第一采样实例上对指定信号进行采样，并且在对应于后续采样边沿的后续采样实例上采样指定信号。
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8.发明申请公开(公告)号：US20060077303A1
公开(公告)日：2006-04-13
申请号：US10964550
申请日：2004-10-13
IPC分类号： H03M1/12
摘要： A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.
摘要翻译： 一种视频解码器，其中1）对于给定位计数模数转换器可以改进分辨率质量，2）可以使用具有基本相似质量的较低位计数模数转换器，或3）改进的组合 可以进行低位数模数转换器的分辨率质量。 在优选实施例中，在已经接收到合成信号的同步部分之后并且在接收到活动视频之前，将DC偏压添加到视频信号。 然后在活动视频周期结束后删除该偏置。 通过施加该偏压，视频信号的直流电压电平实际上被减小，从而也可以减小模数转换处理的满量程值。 因此，与使用无偏信号相比，获得了增加的A / D转换器分辨率。 在替代实施例中，同步部分可以在前部门口向上偏置，然后在后廊期间返回。
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公开(公告)号：US09628906B2
公开(公告)日：2017-04-18
申请号：US13995365
申请日：2012-02-09
CPC分类号： H04R3/00 , H02J7/0042 , H02J7/0055 , H04R2410/00 , Y10T307/858
摘要： An electrical interface circuit includes a microphone circuit, a battery charger circuit and an electrical connector for connecting the electrical interface circuit to an external device. The electrical connector has a pin on which signals are multiplexed for connecting either the battery charger circuit to an external supply voltage, or the microphone circuit to an external microphone. The battery charger circuit includes an amplifying circuit for controlling voltage or current to a battery at battery charging, and a p-type power transistor. The pin is connected to the microphone circuit and to a source of the p-type power transistor. When a voltage applied to the pin exceeds the battery voltage, the p-type power transistor provides current from the pin to the charger circuit, and, otherwise, the charger circuit and battery are disconnected from the pin. A method of multiplexing signals on the electrical interface circuit is also disclosed.
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公开(公告)号：US08787588B2
公开(公告)日：2014-07-22
申请号：US12713083
申请日：2010-02-25
申请人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
发明人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
摘要： Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
摘要翻译： 本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。 在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。 为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。 这些引脚接口由相应的驱动电路驱动。 在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。 这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。
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