公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

申请人： Intel Corporation

发明人： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

摘要： A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US20240222210A1

公开(公告)日：2024-07-04

申请号：US18091548

申请日：2022-12-30

申请人： Intel Corporation

发明人： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC分类号： H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

摘要： An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.

公开(公告)号：US12027470B2

公开(公告)日：2024-07-02

申请号：US17547200

申请日：2021-12-09

申请人： Industrial Technology Research Institute

发明人： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/568 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17

摘要： A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

公开(公告)号：US20240213131A1

公开(公告)日：2024-06-27

申请号：US18089499

申请日：2022-12-27

申请人： Intel Corporation

发明人： Yi YANG ,  Andrew WENTZEL ,  Marcel WALL ,  Suddhasattwa NAD

IPC分类号： H01L23/498 ,  C25D3/38 ,  C25D7/12 ,  C25D17/00 ,  H01L23/15

CPC分类号： H01L23/49827 ,  C25D3/38 ,  C25D7/12 ,  C25D17/001 ,  H01L23/15 ,  H01L24/16 ,  H01L2224/16225

摘要： In an embodiment, a package substrate is described. In an embodiment, the package substrate comprises a layer, where the layer is a dielectric material. In an embodiment, a via opening is provided through a thickness of the layer. In an embodiment, a conductive via is in the via opening, where the conductive via has a substantially uniform composition throughout a thickness of the conductive via. In an embodiment the conductive via directly contacts the layer.

公开(公告)号：US20240186232A1

公开(公告)日：2024-06-06

申请号：US18523906

申请日：2023-11-30

申请人： Absolics Inc.

发明人： Sungjin KIM

IPC分类号： H01L23/498 ,  H01L23/15 ,  H01L23/29 ,  H01L23/31 ,  H05K1/18

CPC分类号： H01L23/49827 ,  H01L23/15 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/49838 ,  H05K1/181

摘要： Embodiments relate to a semiconductor packaging substrate, a semiconductor packages, and a method for manufacturing the semiconductor packaging substrate, wherein a substrate comprising a one surface, other surface facing the one surface, a recessed surface that the one surface recessed, and a side wall connecting the one surface and the recessed surface; and plurality of first vias that penetrating the recessed surface and the other surface; wherein the plurality of first vias include a thermally conductive material. Embodiments have an excellent heat dissipation effect and can prevent warpage on the surface of the substrate due to thermal expansion.

公开(公告)号：US20240178146A1

公开(公告)日：2024-05-30

申请号：US18060080

申请日：2022-11-30

申请人： Intel Corporation

发明人： Benjamin T. Duong ,  Whitney Bryks ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Ravindranath Vithal Mahajan

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L23/15 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13023 ,  H01L2924/15165 ,  H01L2924/15311

摘要： Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

公开(公告)号：US11978685B2

公开(公告)日：2024-05-07

申请号：US16522494

申请日：2019-07-25

申请人： Intel Corporation

发明人： Srinivas Pietambaram ,  Robert L. Sankman ,  Rahul Manepalli ,  Gang Duan ,  Debendra Mallik

IPC分类号： H01L23/15 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/15 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49827 ,  H01L23/5381

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

公开(公告)号：US20240136342A1

公开(公告)日：2024-04-25

申请号：US18404939

申请日：2024-01-05

申请人： Murata Manufacturing Co., Ltd.

发明人： Yukihiro FUJITA ,  Ryutaro YAMATO ,  Tatsuya FUNAKI ,  Yoshiaki SATAKE

IPC分类号： H01L25/10 ,  H01L23/15 ,  H01L23/528 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L25/105 ,  H01L23/15 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/642

摘要： A composite electronic component includes circuit layers, each including an electronic component, that are laminated, first and second circuit layers, a ceramic electronic component between the first and second circuit layers and including via electrodes extending through a body mainly including ceramic and being exposed at a corresponding one of a main surface on one side and a main surface on another side, and a sealing resin covering at least the ceramic electronic component at a location between the first and second circuit layers. At least one electronic component included in each of the first and second circuit layers are electrically connected by the via electrodes.

公开(公告)号：US20240113046A1

公开(公告)日：2024-04-04

申请号：US17957257

申请日：2022-09-30

申请人： Intel Corporation

发明人： Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Benjamin Duong ,  Srinivasan Raman ,  Yi Yang

IPC分类号： H01L23/62 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64

CPC分类号： H01L23/62 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/24 ,  H01L2224/24145 ,  H01L2924/12036

摘要： Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240113009A1

公开(公告)日：2024-04-04

申请号：US17957637

申请日：2022-09-30

申请人： Intel Corporation

发明人： Whitney Bryks ,  Aaditya Candadai ,  Dilan Seneviratne ,  Junxin Wang ,  Peumie Abeyratne Kuragama

IPC分类号： H01L23/498 ,  B05D3/02 ,  B05D3/04 ,  B05D5/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/538

CPC分类号： H01L23/49894 ,  B05D3/0272 ,  B05D3/0426 ,  B05D5/00 ,  H01L21/481 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/5384

摘要： An electronic device can include an interposer, a first porous polymer layer, and one or more die. The interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. The first polymer layer can be adjacent to the first surface of the interposer. The one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.