公开(公告)号：US20110085398A1

公开(公告)日：2011-04-14

申请号：US12577994

申请日：2009-10-13

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1015 ,  G11C11/406 ,  G11C11/40618 ,  G11C2207/229

摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

摘要翻译： 一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。 在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。 随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。 可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。 可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

公开(公告)号：US07870357B2

公开(公告)日：2011-01-11

申请号：US12242870

申请日：2008-09-30

申请人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

发明人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

IPC分类号： G06F12/00

CPC分类号： G11C7/1039 ,  G06F13/1626 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/229

摘要： A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.

摘要翻译： 一种操作包括存储器核心的存储器组件的方法，包括从外部控制线接收指定写入操作的写入命令。 写命令在接收到写命令后第一个时间段被存储。 在第一时间段之后，响应写入命令启动写入操作。 在写入操作期间，接收数据的未屏蔽部分被写入存储器核心，其中数据的未屏蔽部分是由接收到的掩码信息识别为不被掩蔽的数据的位。

公开(公告)号：US07848156B2

公开(公告)日：2010-12-07

申请号：US12055679

申请日：2008-03-26

申请人： Richard E Perego ,  Frederick A Ware

发明人： Richard E Perego ,  Frederick A Ware

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

摘要翻译： 根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。 存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。 存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。 在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。 响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

公开(公告)号：US20090262591A1

公开(公告)日：2009-10-22

申请号：US12497998

申请日：2009-07-06

申请人： Jin-Man Han

发明人： Jin-Man Han

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

摘要： The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

摘要翻译： 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：US07505532B2

公开(公告)日：2009-03-17

申请号：US11604807

申请日：2006-11-28

申请人： Miyoshi Saito ,  Junji Ogawa

发明人： Miyoshi Saito ,  Junji Ogawa

IPC分类号： H04L25/06 ,  H03F3/45

CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

摘要： A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.

摘要翻译： 信号传输系统被构造为通过消除由前面的数据引入的符号间干扰成分，通过信号传输线路传输数据，而不需要为每一位预充电信号传输线。 信号传输线具有以分支结构或层次结构组织的多个可切换信号传输线，从多个信号传输线中的每一个连接至少一个读取数据的目标单元，以及读出电路，包括： 用于消除符号间干扰分量的电路连接到信号传输线，其中，符号间干扰成分消除电路减少了在多个信号传输线之间切换信号传输线时引入的噪声，从而提供平滑的符号间干扰成分消除操作 当信号传输线路被切换时。 这使连续读出成为可能，并实现了信号传输系统的整体速度的提高。

公开(公告)号：US20080005519A1

公开(公告)日：2008-01-03

申请号：US11789712

申请日：2007-04-24

申请人： J. Pawlowski

发明人： J. Pawlowski

IPC分类号： G06F12/00

CPC分类号： G06F12/0207 ,  G06F12/0607 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/229

摘要： Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

摘要翻译： 提供了用于减少多组存储器件中的连续写入和读取访问之间的延迟的系统和方法。 计算机电路修改写访问的地址和数据之间的相对定时，减少连续写入和读取访问之间的延迟。 与这些计算机电路接口的存储器件使用发布的写入访问，以在处理写入访问之前有效地将修改的相对定时返回到其原始时序。

公开(公告)号：US20070279975A1

公开(公告)日：2007-12-06

申请号：US11447821

申请日：2006-06-06

申请人： Stephen J. Hudgens

发明人： Stephen J. Hudgens

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431 ,  G11C2013/0078 ,  G11C2207/229 ,  H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/148

摘要： A phase change memory may be utilized in place of a dynamic random access memory in a processor-based system. In some embodiments, a chalcogenide material, used for the phase change memory, has relatively high crystallization speed so that it may be quickly programmed. Materials may be chosen which have high crystallization speed and corresponding poor data retention. The poor data retention may be compensated by providing a refresh cycle.

摘要翻译： 在基于处理器的系统中可以使用相变存储器代替动态随机存取存储器。 在一些实施方案中，用于相变存储器的硫族化物材料具有相对高的结晶速度，使得其可以被快速编程。 可以选择具有高结晶速度和相应差的数据保留性的材料。 可以通过提供刷新周期来补偿差的数据保留。

公开(公告)号：US07290117B2

公开(公告)日：2007-10-30

申请号：US10032109

申请日：2001-12-20

申请人： Erik E. Erlandson ,  David A. Tremblay, Jr.

发明人： Erik E. Erlandson ,  David A. Tremblay, Jr.

IPC分类号： G06F12/00 ,  G06F8/00

CPC分类号： G11C7/1021 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address. Or, the comparator can compare the external or internal address to a predetermined end address, and the memory can terminate the cycle when the external or internal address equals the end address.

摘要翻译： 存储器包括地址总线，地址计数器，地址解码器，比较器和控制电路。 在数据读或写周期期间，地址总线接收外部地址，地址计数器产生一个内部地址，地址解码器解码，比较器将外部地址与一个值进行比较。 基于外部地址和值之间的关系，比较器启用或禁用数据传输。 例如，这样的存储器可以通过确定当前外部列地址何时不再等于当前内部列地址来终止页模式读/写周期。 这允许系统通过将外部列地址设置为不等于内部列地址的值来在预定数量的数据传输之后终止循环。 或者，比较器可以将外部或内部地址与预定的结束地址进行比较，并且当外部或内部地址等于结束地址时，存储器可以终止循环。

公开(公告)号：US07251176B2

公开(公告)日：2007-07-31

申请号：US11490234

申请日：2006-07-21

申请人： Yasuyuki Kajitani ,  Daisuke Kato

发明人： Yasuyuki Kajitani ,  Daisuke Kato

IPC分类号： G11C7/02

CPC分类号： G11C29/50008 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/10897

摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.

摘要翻译： 一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对， 设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门， 在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路 多个可变电阻元件。

公开(公告)号：US07196941B2

公开(公告)日：2007-03-27

申请号：US10798469

申请日：2004-03-11

申请人： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

发明人： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C7/10 ,  G11C7/1021 ,  G11C7/1048 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

摘要翻译： 一种半导体存储器件和用于从其读取和读取数据的方法包括：存储单元阵列，包括连接在多个字线和多个位线对之间的多个存储器单元，预定数量的写入线对 ，预定数量的读线对，用于在写入操作期间在多个位线对与预定数量的写入线对之间传送数据的多个写入列选择门和用于发送数据的多个读取列选择门 在读取操作期间在多个位线对与预定数量的读取线对之间。 因此，可以通过数据输入焊盘和数据输出焊盘同时输入和输出数据。