公开(公告)号：US5828985A

公开(公告)日：1998-10-27

申请号：US754230

申请日：1996-11-20

Applicant: Robert F. Sauer ,  Jun Makino ,  Hiroaki Yamoto

Inventor： Robert F. Sauer ,  Jun Makino ,  Hiroaki Yamoto

IPC: G01R31/319 ,  G06F11/00

CPC classification number: G01R31/31903 ,  G06F2201/865

Abstract: A software structure in a semiconductor test system for easily modifying and transferring data for controlling a hardware when the hardware is changed or replaced. The semiconductor test system includes, an input for providing a test program for specifying various test conditions necessary to test the semiconductor device under test, a master processor for converting the test program to an object code and interpreting the contents of the test program, a processor interface for storing data indicating the hardware characteristics of the semiconductor test system in a table format to assist the interpretation of the test program in the master processor and modifying the table format data in response to the change in the hardware, a library having data tables based on the specification of the semiconductor test system for converting the format of the data compiled and interpreted by the master processor to data of a hardware format, and a driver for transmitting the hardware format data to registers in the hardware of the semiconductor test system through a data bus.

Abstract translation: 半导体测试系统中的软件结构，用于在硬件改变或更换时容易地修改和传送用于控制硬件的数据。 半导体测试系统包括：用于提供用于指定测试被测半导体器件所需的各种测试条件的测试程序的输入，用于将测试程序转换为目标代码并解释测试程序的内容的主处理器，处理器 接口，用于以表格格式存储指示半导体测试系统的硬件特性的数据，以帮助解释主处理器中的测试程序，并响应于硬件的变化修改表格格式数据，具有基于数据表的库 关于用于将由主处理器编译和解释的数据的格式转换为硬件格式的数据的半导体测试系统的规范，以及用于通过以下方式将硬件格式数据发送到半导体测试系统的硬件中的寄存器的驱动器： 数据总线。

公开(公告)号：US4706208A

公开(公告)日：1987-11-10

申请号：US772157

申请日：1985-09-03

Applicant: Howard D. Helms

Inventor： Howard D. Helms

IPC: G01R31/319 ,  G06F11/30 ,  G05B23/02

CPC classification number: G01R31/31903

Abstract: The present invention relates to an Operational Life Test (OLT) or "burn-in" technique for testing microprocessors. In accordance with the present invention, an OLT chamber is provided wherein many Evaluation Boards are mounted within racks in a frame in the chamber, each Board being designed for separately exercising its associated microprocessor integrated circuit (IC). During the OLT or burn-in procedure, each Evaluation Boards runs its own internally stored diagnostics, simultaneously with other Boards, to exercise the associated microprocessor ICs while the power to the Boards and the environment within the chamber is appropriately cycled to simulate system testing, installation or normal customer use. During the OLT procedure, each Board periodically reports the status of the associated microprocessor IC to circuitry such as a computer outside the chamber in order to provide a means for determining and recording any failure of a Board.

Abstract translation: 本发明涉及用于测试微处理器的操作寿命测试（OLT）或“老化”技术。 根据本发明，提供了一个OLT室，其中许多评估板安装在腔室中的框架内的机架中，每个板被设计用于分别运行其相关的微处理器集成电路（IC）。 在OLT或老化过程中，每个评估板与其他板同时运行自己的内部存储的诊断程序来运行相关的微处理器IC，同时适当地循环对板内的电源和室内的环境进行系统测试， 安装或普通客户使用。 在OLT程序期间，每个主板周期性地将关联的微处理器IC的状态报告给诸如室外的计算机的电路，以便提供用于确定和记录板的任何故障的装置。

公开(公告)号：US20180356465A1

公开(公告)日：2018-12-13

申请号：US16060524

申请日：2015-12-18

Applicant: ZURICH INSTRUMENTS AG

Inventor： Niels HAANDBAEK ,  Flavio HEER ,  Stephan KOCH ,  Sadik HAFIZOVIC

IPC: G01R31/319

CPC classification number: G01R31/31903 ,  G01R15/12

Abstract: A device for dynamic signal generation and analysis, which combines an arbitrary waveform generator AWG (3) with a digital signal analysis unit DSAU (23). The two units are interfaced by means of a synchronization unit SU (30), which enables a flexible scheme for controlling how the playback of the waveforms is started as well as synchronizing the recording of the results of the digital signal analysis unit synchronously to specific generated waveforms. The various units of the device are synchronous circuits clocked by a common system clock signal. At least one common numerically controlled oscillator NCO (40) is provided for the arbitrary waveform generator AWG (3) and the digital signal analysis unit DSAU (23).

公开(公告)号：US10061673B2

公开(公告)日：2018-08-28

申请号：US15292586

申请日：2016-10-13

Applicant: Primax Electronics Ltd.

Inventor： Pei-Ming Chang ,  Shih-Chieh Hsu ,  Shi-Jie Zhang ,  Wei-Lung Huang

IPC: G06F11/263 ,  G01R31/319 ,  G01R31/26 ,  G06F11/273 ,  G01R31/28 ,  G06F9/4401 ,  G06F13/362

CPC classification number: G06F11/263 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2806 ,  G01R31/2851 ,  G01R31/319 ,  G01R31/31903 ,  G06F9/4408 ,  G06F11/273 ,  G06F11/2733 ,  G06F13/362 ,  Y02P90/30

Abstract: A testing system uses different operating systems to test electronic products. The testing system includes a master computer, a slave computer and a relay. A first operating system is installed in the master computer. A second operating system is installed in the slave computer. The master computer and the slave computer are connected with each other through RS-232 ports. The relay is connected with the master computer, the slave computer and an under-test product. By changing the voltage level state of specified pins of the RS-232 ports, the master computer notifies the slave computer to test the under-test product. Moreover, by controlling the relay, the connection between the master computer and the under-test product is switched to the connection between the slave computer and the under-test product. Consequently, the under-test product is tested by the slave computer.

公开(公告)号：US20180196103A1

公开(公告)日：2018-07-12

申请号：US15914553

申请日：2018-03-07

Applicant: Advantest Corporation

Inventor： Duane CHAMPOUX ,  Mei-Mei SU

IPC: G01R31/317

CPC classification number: G01R31/31724 ,  G01R31/2601 ,  G01R31/31723 ,  G01R31/31903 ,  G01R31/31907 ,  G01R31/31908 ,  G01R31/31919 ,  G01R35/00 ,  G06F11/263

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

公开(公告)号：US20170285105A1

公开(公告)日：2017-10-05

申请号：US15512098

申请日：2015-07-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Katsunari UEMURA ,  Shohei YAMADA ,  Hidekazu TSUBOI

IPC: G01R31/319 ,  H04W24/00 ,  G06F11/36 ,  H04L12/54 ,  H04B7/06 ,  H04M9/02

CPC classification number: G01R31/31903 ,  G06F11/3656 ,  H04B7/061 ,  H04L12/5692 ,  H04M9/027 ,  H04W24/00 ,  H04W28/06 ,  H04W72/02 ,  H04W72/042 ,  H04W76/14 ,  H04W92/18

Abstract: Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.

公开(公告)号：US20160119218A1

公开(公告)日：2016-04-28

申请号：US14574137

申请日：2014-12-17

Applicant: TEKTRONIX, INC.

Inventor： EDWARD F. TANOUS ,  KEITH D. RULE ,  JAMES FEIST

IPC: H04L12/26

CPC classification number: H04L43/50 ,  G01R31/31903 ,  G11C29/56 ,  H04L43/04 ,  H04L43/12

Abstract: A test-and-measurement instrument is described. The test-and-measurement instrument can store a state machine. As the state machine is used to analyze a bit stream, breadcrumbs can be saved from states in a memory of the state machine. The breadcrumbs can then be used to analyze the operation of the state machine.

Abstract translation: 描述了测试和测量仪器。 测试和测量仪器可以存储状态机。 由于状态机用于分析位流，所以可以从状态机的存储器中的状态保存面包屑。 然后可以使用面包屑来分析状态机的操作。

公开(公告)号：US20160070631A1

公开(公告)日：2016-03-10

申请号：US14783405

申请日：2014-04-04

Applicant: EADS DEUTSCHLAND GMBH

Inventor： Philipp WAGER ,  Bernd SCHUMACHER

IPC: G06F11/30 ,  G01R31/319

CPC classification number: G06F11/3041 ,  G01R31/2834 ,  G01R31/31903 ,  G01R31/31907 ,  G06F11/273 ,  G06F11/3664

Abstract: The present invention relates to an arrangement for providing a test environment for testing test objects. The arrangement includes a first test case implementation unit and a second test case implementation unit, as well as a first test object and a second test object. In one embodiment, the test environment is configured such that at least the first test case implementation unit is coupled to at least one of the first test object and the second test object for implementing a test case.

Abstract translation: 本发明涉及一种用于提供测试对象测试环境的装置。 该装置包括第一测试用例实现单元和第二测试用例实现单元，以及第一测试对象和第二测试对象。 在一个实施例中，测试环境被配置为使得至少第一测试用例实现单元耦合到第一测试对象和第二测试对象中的至少一个以实现测试用例。

公开(公告)号：US09274911B2

公开(公告)日：2016-03-01

申请号：US13773559

申请日：2013-02-21

Applicant: Advantest Corporation

Inventor： Mark Elston ,  Harsanjeet Singh ,  Ankan Pramanick ,  Leon Lee Chen ,  Hironori Maeda ,  Chandra Pinjala ,  Ramachandran Krishnaswamy

IPC: G01R31/319 ,  G01R31/28 ,  G06F11/26 ,  G06F11/263

CPC classification number: G06F11/26 ,  G01R31/2834 ,  G01R31/31903 ,  G01R31/31907 ,  G01R31/31908 ,  G01R31/31926 ,  G06F11/263

Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract translation: 公开了一种在并发测试执行环境中使用共享引脚的方法。 该方法涉及同时执行自动化测试设备（ATE）的测试流程中的调度测试，以便能够在测试流之间共享资源。 该方法包括确定由第一测试使用的多个分裂中的任一个是否包含至少一个共享的资源，其中第一测试和第二测试被排序以在两个单独的并发执行的测试流中执行。 所述方法还包括：如果所述拆分与所述第二和第二测试所需的资源相关联，则确定在所述第二测试之前是否应执行所述第一测试。 最后，该方法包括在开始执行第一测试之前，先保留包含至少一个共享资源的拆分以进行第一次测试。

公开(公告)号：US08838406B2

公开(公告)日：2014-09-16

申请号：US13128705

申请日：2008-11-11

Applicant: Jochen Rivoir

Inventor： Jochen Rivoir

IPC: G06F19/00 ,  G01R31/319 ,  G01R31/3185

CPC classification number: G01R31/2834 ,  G01R31/318533 ,  G01R31/31903 ,  G01R31/31908 ,  G01R31/31926

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract translation: 用于自动测试设备的可重新配置的测试电路包括测试电路，测试处理器和可编程逻辑器件。 引脚电子电路被配置为将可重新配置的测试电路与DUT连接。 测试处理器包括定时电路，其被配置为提供具有可调定时的一个或多个可调定时信号。 可编程逻辑器件被配置为实现其状态序列取决于从引脚电子电路接收的一个或多个输入信号的状态机，以提供取决于状态机的当前状态或先前状态的输出信号， 响应于从引脚电子电路接收的信号到引脚电子电路。 测试处理器耦合到可编程逻辑器件，以向可编程逻辑器件提供可调整定时信号中的至少一个以定义可编程逻辑器件的定时。