公开(公告)号：US20060076619A1

公开(公告)日：2006-04-13

申请号：US11283015

申请日：2005-11-18

Applicant: Hongmei Wang ,  Zhongze Wang

Inventor： Hongmei Wang ,  Zhongze Wang

IPC: H01L29/76

CPC classification number: H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

Abstract: The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

Abstract translation: 本发明提供了一种制造MOSFET中的电介质塞的技术。 本发明包括包括一个或多个器件的器件和系统，该器件和系统包括具有电介质插塞的MOSFET。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底，并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。

公开(公告)号：US07012293B2

公开(公告)日：2006-03-14

申请号：US10379480

申请日：2003-03-04

Applicant: Zhongze Wang

Inventor： Zhongze Wang

IPC: H01L29/76

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: The present invention provides an improved SRAM cell design. The SRAM cell includes a first active area on oxide in a first conductive well located on a first vertical side of the SRAM cell, a second active area on oxide in a second conductive well located on the first vertical side of the SRAM cell, a third active area on oxide in the first conductive well located on a second vertical side of the SRAM cell, a fourth active area on oxide in the second conductive well located on the second vertical side of the SRAM cell, a first gate located on the first vertical side of the SRAM cell, a second gate located on the second vertical side of the SRAM cell, a first local interconnect connecting the first active area, the second active area, and the second gate via a second EC contact located on the second gate, and a second local interconnect connecting the third active area, the fourth active area, and the first gate via a first EC contact located on the first gate.

Abstract translation: 本发明提供了一种改进的SRAM单元设计。 SRAM单元包括位于SRAM单元的第一垂直侧的第一导电阱中的氧化物上的第一有源区，位于SRAM单元的第一垂直侧的第二导电阱中的氧化物上的第二有源区， 位于SRAM单元的第二垂直侧的第一导电阱中的氧化物上的有源区，位于SRAM单元的第二垂直侧的第二导电阱中的氧化物上的第四有源区，位于第一垂直方向上的第一栅极 位于SRAM单元的第二垂直侧的第二栅极，经由位于第二栅极上的第二EC触点连接第一有源区域，第二有源区域和第二栅极的第一局部互连， 以及经由位于第一门上的第一EC触点连接第三有源区域，第四有源区域和第一栅极的第二局部互连。

公开(公告)号：US06927473B2

公开(公告)日：2005-08-09

申请号：US10620054

申请日：2003-07-14

Applicant: Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

Inventor： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers, an overlying and underlying layer, on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract translation: 用于集成电路和半导体器件的保险丝，其制造和使用的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

公开(公告)号：US20050098828A1

公开(公告)日：2005-05-12

申请号：US11013377

申请日：2004-12-17

Applicant: Zhongze Wang

Inventor： Zhongze Wang

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/66772 ,  H01L21/76256 ,  H01L29/78603

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

公开(公告)号：US20050048746A1

公开(公告)日：2005-03-03

申请号：US10651314

申请日：2003-08-28

Applicant: Zhongze Wang

Inventor： Zhongze Wang

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/76 ,  H01L21/336 ,  H01L21/425

CPC classification number: H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

公开(公告)号：US06417546B2

公开(公告)日：2002-07-09

申请号：US09444024

申请日：1999-11-19

Applicant: Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

Inventor： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC: H01L2994

CPC classification number: H01L21/823462

Abstract: In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

Abstract translation: 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US6162693A

公开(公告)日：2000-12-19

申请号：US389295

申请日：1999-09-02

Applicant: Zhongze Wang ,  Rongsheng Yang

Inventor： Zhongze Wang ,  Rongsheng Yang

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66537 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66575

Abstract: A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

公开(公告)号：US6093661A

公开(公告)日：2000-07-25

申请号：US386076

申请日：1999-08-30

Applicant: Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

Inventor： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC: H01L21/8234 ,  H01L21/31 ,  H01L21/336

CPC classification number: H01L21/823462

Abstract: In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

公开(公告)号：US09875788B2

公开(公告)日：2018-01-23

申请号：US12731668

申请日：2010-03-25

Applicant: Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

Inventor： Seong-Ook Jung ,  Hyunkook Park ,  Seung-Chul Song ,  Mohamed Hassan Abu-Rahma ,  Lixin Ge ,  Zhongze Wang ,  Beom-Mo Han

IPC: G11C11/412

CPC classification number: G11C11/412

Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

公开(公告)号：US20140070364A1

公开(公告)日：2014-03-13

申请号：US13613008

申请日：2012-09-13

Applicant: Yong Park ,  Zhongze Wang ,  John J. Zhu ,  Choh Fei Yeap

Inventor： Yong Park ,  Zhongze Wang ,  John J. Zhu ,  Choh Fei Yeap

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/101 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.

Abstract translation: 电可编程栅极氧化物反熔丝器件包括具有抗熔丝链路的抗熔丝孔，所述抗熔丝孔包括其间具有介电层的金属和/或半导体电极。 介电层可以是层间电介质（ILD），金属间电介质（IMD）或蚀刻停止层。 反熔丝器件可以包括具有设置在衬底的表面上的导电栅极（例如，高K金属栅极）和设置在导电栅极上的介电层的半导体衬底。 堆叠的触点可以设置在电介质层上，并且栅极触点设置在栅极的暴露部分上。