公开(公告)号：US11984817B2

公开(公告)日：2024-05-14

申请号：US16814626

申请日：2020-03-10

Applicant: XILINX, INC.

Inventor： Junho Cho ,  Kevin Zheng ,  Parag Upadhyaya

IPC: H02M7/483

CPC classification number: H02M7/483 ,  H02M7/4835

Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.

公开(公告)号：US11108401B2

公开(公告)日：2021-08-31

申请号：US16688130

申请日：2019-11-19

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun Ma

IPC: H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  G06F1/08 ,  H03B5/12 ,  H04L7/033 ,  H03L7/083 ,  H04L27/00 ,  H03F3/24 ,  H03F3/21

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：US10559561B2

公开(公告)日：2020-02-11

申请号：US15875568

申请日：2018-01-19

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H01L21/00 ,  H01L27/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/64

Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

公开(公告)号：US10536151B1

公开(公告)日：2020-01-14

申请号：US16024473

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Jinyung Namkoong ,  Stanley Y. Chen ,  Parag Upadhyaya

IPC: H03L7/08 ,  G06F1/06 ,  H03K3/03

Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

公开(公告)号：US10224937B1

公开(公告)日：2019-03-05

申请号：US15959104

申请日：2018-04-20

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Geoffrey Zhang ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H03L7/08 ,  H04L7/00 ,  H04L1/00 ,  H03L7/197 ,  H03L7/099 ,  H04L7/033

Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

公开(公告)号：US20180190584A1

公开(公告)日：2018-07-05

申请号：US15397612

申请日：2017-01-03

Applicant: Xilinx, Inc.

Inventor： Parag Upadhyaya ,  Jing Jing

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H03B5/12

CPC classification number: H01L23/5225 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L29/402 ,  H03B5/1215 ,  H03B2201/0208

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.

公开(公告)号：US09954539B2

公开(公告)日：2018-04-24

申请号：US15206634

申请日：2016-07-11

Applicant: Xilinx, Inc.

Inventor： Jinyung Namkoong ,  Mayank Raj ,  Parag Upadhyaya ,  Vamshi Manthena ,  Catherine Hearne ,  Marc Erett

IPC: H03L7/06 ,  H03L7/089 ,  H03M9/00

CPC classification number: H03L7/0891 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/24 ,  H03M9/00

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

公开(公告)号：US20170244371A1

公开(公告)日：2017-08-24

申请号：US15049963

申请日：2016-02-22

Applicant: Xilinx, Inc.

Inventor： Didem Z. Turker Melek ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H03G3/30 ,  H03F3/16 ,  H04B1/12 ,  H03F1/02

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/0211 ,  H03F3/16 ,  H03F3/45197 ,  H03F2200/555 ,  H03F2203/45492 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/301 ,  H04B1/123 ,  H04L25/03885

Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

公开(公告)号：US20170134009A1

公开(公告)日：2017-05-11

申请号：US14933346

申请日：2015-11-05

Applicant: Xilinx, Inc.

Inventor： Jinyung Namkoong ,  Wenfeng Zhang ,  Parag Upadhyaya

IPC: H03K3/01

CPC classification number: H03K3/01 ,  H03K19/017527

Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

公开(公告)号：US20160322979A1

公开(公告)日：2016-11-03

申请号：US14700695

申请日：2015-04-30

Applicant: Xilinx, Inc.

Inventor： Parag Upadhyaya ,  Adebabay M. Bekele ,  Didem Z. Turker Melek ,  Zhaoyin D. Wu

IPC: H03L7/095 ,  H04B1/50 ,  H03M3/00

CPC classification number: H03L7/095 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03M3/30 ,  H04B1/50

Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Abstract translation: 在一个示例中，锁相环（PLL）电路包括可操作以产生误差信号的误差检测器; 振荡器，其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是频率乘数乘以参考频率; 分频器，用于将输出信号的输出频率除以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM），可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述SDM的次序的订单选择信号; 以及状态机，其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。