公开(公告)号：US11282775B1

公开(公告)日：2022-03-22

申请号：US16942930

申请日：2020-07-30

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L21/768 ,  H01L21/683 ,  H01L23/31

Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.

公开(公告)号：US11127643B1

公开(公告)日：2021-09-21

申请号：US16588253

申请日：2019-09-30

Applicant: Xilinx, Inc.

Inventor： Vadim Heyfitch ,  Jaspreet Singh Gandhi

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/00

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.

公开(公告)号：US10930611B1

公开(公告)日：2021-02-23

申请号：US16523950

申请日：2019-07-26

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Tien-Yu Lee

IPC: H01L23/00

Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.

公开(公告)号：US10236229B2

公开(公告)日：2019-03-19

申请号：US15192235

申请日：2016-06-24

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi

IPC: H01L23/04 ,  H01L23/13 ,  H01L23/367 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/373

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.

公开(公告)号：US20170372979A1

公开(公告)日：2017-12-28

申请号：US15192235

申请日：2016-06-24

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi

IPC: H01L23/13 ,  H01L23/58 ,  H01L23/367 ,  H01L25/065 ,  H01L23/04

CPC classification number: H01L23/13 ,  H01L23/04 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.

公开(公告)号：US12027493B2

公开(公告)日：2024-07-02

申请号：US16672802

申请日：2019-11-04

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L24/05 ,  H01L2021/60007 ,  H01L2224/02371 ,  H01L2224/02372

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

公开(公告)号：US11901300B2

公开(公告)日：2024-02-13

申请号：US17677899

申请日：2022-02-22

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Brian C. Gaide

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/06 ,  H01L25/18 ,  H01L2224/0612

Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.

公开(公告)号：US11488936B2

公开(公告)日：2022-11-01

申请号：US16718868

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/04 ,  H01L23/31

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

公开(公告)号：US11195780B1

公开(公告)日：2021-12-07

申请号：US16828822

申请日：2020-03-24

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L31/12 ,  H01L23/427 ,  H01L23/373 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/10

Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.

公开(公告)号：US11145566B2

公开(公告)日：2021-10-12

申请号：US16786447

申请日：2020-02-10

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L25/065

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die. A first conductive heat transfer structure of the plurality of electrically floating conductive heat transfer structures are part of a first conductive heat transfer path having a length in the first direction at least as long as a distance between the first and second surfaces.